Fsp1.1 update.

[mirror_edk2.git] / IntelFspPkg / IntelFspPkg.dec

diff --git a/IntelFspPkg/IntelFspPkg.dec b/IntelFspPkg/IntelFspPkg.dec
index ef942a7ac4e389de871a2b85e5f3571bf44699c5..1f286c1c7d945202646ed55e070c8239a7f315d4 100644 (file)
--- a/IntelFspPkg/IntelFspPkg.dec
+++ b/IntelFspPkg/IntelFspPkg.dec
@@ -1,8 +1,7 @@
 ## @file\r
-#\r
 # Provides driver and definitions to build fsp in EDKII bios.\r
 #\r
-# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
 # This program and the accompanying materials are licensed and made available under\r
 # the terms and conditions of the BSD License that accompanies this distribution.\r
 # The full text of the license may be found at\r
@@ -21,11 +20,52 @@
 \r
 [Includes]\r
   Include\r
+  Include/Private\r
+  \r
+[LibraryClasses]\r
+  ##  @libraryclass  Provides cache-as-ram support.\r
+  CacheAsRamLib|IntelFspPkg/Include/Library/CacheAsRamLib.h\r
+\r
+  ##  @libraryclass  Provides cache setting on MTRR.\r
+  CacheLib|IntelFspPkg/Include/Library/CacheLib.h\r
+\r
+  ##  @libraryclass  Provides debug device abstraction.\r
+  DebugDeviceLib|IntelFspPkg/Include/Library/DebugDeviceLib.h\r
+\r
+  ##  @libraryclass  Provides FSP related services.\r
+  FspCommonLib|IntelFspPkg/Include/Library/FspCommonLib.h\r
+\r
+  ##  @libraryclass  Provides FSP platform related actions.\r
+  FspPlatformLib|IntelFspPkg/Include/Library/FspPlatformLib.h\r
+\r
+  ##  @libraryclass  Provides FSP switch stack function.\r
+  FspSwitchStackLib|IntelFspPkg/Include/Library/FspSwitchStackLib.h\r
 \r
 [Guids]\r
+  #\r
+  # GUID defined in package\r
+  #\r
+  gIntelFspPkgTokenSpaceGuid           = { 0x834c0c5f, 0xadb3, 0x4372, { 0xae, 0xeb, 0x03, 0xe4, 0xe9, 0xe6, 0xc5, 0x91 } }\r
+\r
   # Guid define in FSP EAS\r
   gFspHeaderFileGuid                    = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
   gFspBootLoaderTemporaryMemoryGuid     = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }\r
   gFspReservedMemoryResourceHobGuid     = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
   gFspNonVolatileStorageHobGuid         = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
 \r
+  # Guid defined by platform\r
+  gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }\r
+  gFspReservedMemoryResourceHobGfxGuid  = { 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } }\r
+  gFspReservedMemoryResourceHobMiscGuid = { 0x00d6b14b, 0x7dd0, 0x4062, { 0x88, 0x21, 0xe5, 0xf9, 0x6a, 0x2a, 0x1b, 0x00 } }\r
+\r
+[PcdsFixedAtBuild]\r
+  gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00108|UINT32|0x00000001\r
+  gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase        |0xFEF00000|UINT32|0x10001001\r
+  gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize        |    0x2000|UINT32|0x10001002\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize     |    0x1000|UINT32|0x10001003\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry         |        32|UINT32|0x00002001\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry        |         5|UINT32|0x00002002\r
+\r
+[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
+  gIntelFspPkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r
+  gIntelFspPkgTokenSpaceGuid.PcdBootLoaderEntry         |0xFFFFFFE4|UINT32|0x46530100\r