Add IntelFspPkg to support create FSP bin based on EDKII.

[mirror_edk2.git] / IntelFspPkg / Library / BaseCacheLib / CacheLibInternal.h

diff --git a/IntelFspPkg/Library/BaseCacheLib/CacheLibInternal.h b/IntelFspPkg/Library/BaseCacheLib/CacheLibInternal.h
new file mode 100644 (file)
index 0000000..fbbf551
--- /dev/null
+++ b/IntelFspPkg/Library/BaseCacheLib/CacheLibInternal.h
@@ -0,0 +1,59 @@
+/** @file\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _CACHE_LIB_INTERNAL_H_\r
+#define _CACHE_LIB_INTERNAL_H_\r
+\r
+#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE       0x00000200\r
+#define EFI_MSR_CACHE_VARIABLE_MTRR_END        0x0000020F\r
+#define   V_EFI_FIXED_MTRR_NUMBER                                      11\r
+\r
+#define EFI_MSR_IA32_MTRR_FIX64K_00000         0x00000250\r
+#define EFI_MSR_IA32_MTRR_FIX16K_80000         0x00000258\r
+#define EFI_MSR_IA32_MTRR_FIX16K_A0000         0x00000259\r
+#define EFI_MSR_IA32_MTRR_FIX4K_C0000          0x00000268\r
+#define EFI_MSR_IA32_MTRR_FIX4K_C8000          0x00000269\r
+#define EFI_MSR_IA32_MTRR_FIX4K_D0000          0x0000026A\r
+#define EFI_MSR_IA32_MTRR_FIX4K_D8000          0x0000026B\r
+#define EFI_MSR_IA32_MTRR_FIX4K_E0000          0x0000026C\r
+#define EFI_MSR_IA32_MTRR_FIX4K_E8000          0x0000026D\r
+#define EFI_MSR_IA32_MTRR_FIX4K_F0000          0x0000026E\r
+#define EFI_MSR_IA32_MTRR_FIX4K_F8000          0x0000026F\r
+#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE       0x000002FF\r
+#define   B_EFI_MSR_CACHE_MTRR_VALID                                   BIT11\r
+#define   B_EFI_MSR_GLOBAL_MTRR_ENABLE                                 BIT11\r
+#define   B_EFI_MSR_FIXED_MTRR_ENABLE                                  BIT10\r
+#define   B_EFI_MSR_CACHE_MEMORY_TYPE                                  (BIT2 | BIT1 | BIT0)\r
+\r
+#define EFI_MSR_VALID_MASK                     0xFFFFFFFFF\r
+#define EFI_CACHE_VALID_ADDRESS                0xFFFFFF000\r
+#define EFI_SMRR_CACHE_VALID_ADDRESS           0xFFFFF000\r
+#define EFI_CACHE_VALID_EXTENDED_ADDRESS       0xFFFFFFFFFF000\r
+\r
+// Leave one MTRR pairs for OS use\r
+#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS   1\r
+#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \\r
+        (EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2)\r
+\r
+#define EFI_MSR_IA32_MTRR_CAP                  0x000000FE\r
+#define   B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT                         BIT12\r
+#define   B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT                         BIT11\r
+#define   B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT                           BIT10\r
+#define   B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT                        BIT8\r
+#define   B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT                     (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)\r
+\r
+#define CPUID_VIR_PHY_ADDRESS_SIZE                                    0x80000008\r
+#define CPUID_EXTENDED_FUNCTION                                       0x80000000\r
+\r
+#endif\r
+\r