Add IntelFspWrapper to support boot EDKII on FSP bin.

[mirror_edk2.git] / IntelFspWrapperPkg / Library / SecPeiFspPlatformSecLibSample / Ia32 / AsmSaveSecContext.S

diff --git a/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/AsmSaveSecContext.S b/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/AsmSaveSecContext.S
new file mode 100644 (file)
index 0000000..3838cc8
--- /dev/null
+++ b/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/AsmSaveSecContext.S
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+#  AsmSaveSecContext.S\r
+#\r
+# Abstract:\r
+#\r
+#   Save Sec Conext before call FspInit API\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#----------------------------------------------------------------------------\r
+#  MMX Usage:\r
+#              MM0 = BIST State\r
+#              MM5 = Save time-stamp counter value high32bit\r
+#              MM6 = Save time-stamp counter value low32bit.\r
+#\r
+#  It should be same as SecEntry.asm and PeiCoreEntry.asm.\r
+#----------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(AsmSaveBistValue)\r
+ASM_PFX(AsmSaveBistValue):\r
+  movl    4(%esp), %eax\r
+  movd    %eax, %mm0\r
+  ret\r
+\r
+ASM_GLOBAL ASM_PFX(AsmSaveTickerValue)\r
+ASM_PFX(AsmSaveTickerValue):\r
+  movl    4(%esp), %eax\r
+  movd    %eax, %mm6\r
+  movl    8(%esp), %eax\r
+  movd    %eax, %mm5\r
+  ret\r