IntelSiliconPkg IntelVTdDxe: Fix flush cache issue

[mirror_edk2.git] / IntelSiliconPkg / Feature / VTd / IntelVTdDxe / TranslationTable.c

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index 7bdc4a5146bd88f56fda72106fdcedcbf09b5a99..bce5a45105d2f97eba408f5209b073f453fc2616 100644 (file)
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -1,6 +1,6 @@
 /** @file\r
 \r
 /** @file\r
 \r

-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -226,7 +226,7 @@ CreateSecondLevelPagingEntryTable (
 \r
     Lvl3Start = RShiftU64 (BaseAddress, 30) & 0x1FF;\r
     if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <= EndAddress) {\r
 \r
     Lvl3Start = RShiftU64 (BaseAddress, 30) & 0x1FF;\r
     if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <= EndAddress) {\r

-      Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY);\r
+      Lvl3End = SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) - 1;\r

     } else {\r
       Lvl3End = RShiftU64 (EndAddress - 1, 30) & 0x1FF;\r
     }\r
     } else {\r
       Lvl3End = RShiftU64 (EndAddress - 1, 30) & 0x1FF;\r
     }\r


@@ -252,16 +252,21 @@ CreateSecondLevelPagingEntryTable (
         Lvl2PtEntry[Index2].Bits.PageSize = 1;\r
         BaseAddress += SIZE_2MB;\r
         if (BaseAddress >= MemoryLimit) {\r
         Lvl2PtEntry[Index2].Bits.PageSize = 1;\r
         BaseAddress += SIZE_2MB;\r
         if (BaseAddress >= MemoryLimit) {\r

-          goto Done;\r
+          break;\r

         }\r
       }\r
       FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB);\r
         }\r
       }\r
       FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB);\r

+      if (BaseAddress >= MemoryLimit) {\r
+        break;\r
+      }\r

     }\r
     FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], (UINTN)&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]);\r
     }\r
     FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], (UINTN)&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]);\r

+    if (BaseAddress >= MemoryLimit) {\r
+      break;\r
+    }\r

   }\r
   FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], (UINTN)&Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]);\r
 \r
   }\r
   FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], (UINTN)&Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]);\r
 \r

-Done:\r

   return SecondLevelPagingEntry;\r
 }\r
 \r
   return SecondLevelPagingEntry;\r
 }\r
 \r