--- /dev/null
+/** @file\r
+ IGD OpRegion definition from Intel Integrated Graphics Device OpRegion\r
+ Specification.\r
+\r
+ https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf\r
+\r
+ There are some mismatch between the specification and the implementation.\r
+ The definition follows the latest implementation.\r
+ 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]\r
+ 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]\r
+ 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]\r
+ 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1C00]\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef _IGD_OPREGION_H_\r
+#define _IGD_OPREGION_H_\r
+\r
+/**\r
+ OpRegion structures:\r
+ Sub-structures define the different parts of the OpRegion followed by the\r
+ main structure representing the entire OpRegion.\r
+\r
+ Note: These structures are packed to 1 byte offsets because the exact\r
+ data location is requred by the supporting design specification due to\r
+ the fact that the data is used by ASL and Graphics driver code compiled\r
+ separatly.\r
+**/\r
+#pragma pack(1)\r
+///\r
+/// OpRegion header (mailbox 0) structure and defines.\r
+///\r
+typedef struct {\r
+ CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion Signature\r
+ UINT32 SIZE; ///< Offset 16 OpRegion Size\r
+ UINT32 OVER; ///< Offset 20 OpRegion Structure Version\r
+ UINT8 SVER[0x20]; ///< Offset 24 System BIOS Build Version\r
+ UINT8 VVER[0x10]; ///< Offset 56 Video BIOS Build Version\r
+ UINT8 GVER[0x10]; ///< Offset 72 Graphic Driver Build Version\r
+ UINT32 MBOX; ///< Offset 88 Supported Mailboxes\r
+ UINT32 DMOD; ///< Offset 92 Driver Model\r
+ UINT8 RSV1[0xA0]; ///< Offset 96 Reserved\r
+} INTEL_IGD_OPREGION_HEADER;\r
+\r
+///\r
+/// OpRegion mailbox 1 (public ACPI Methods).\r
+///\r
+typedef struct {\r
+ UINT32 DRDY; ///< Offset 0 Driver Readiness\r
+ UINT32 CSTS; ///< Offset 4 Status\r
+ UINT32 CEVT; ///< Offset 8 Current Event\r
+ UINT8 RSV2[0x14]; ///< Offset 12 Reserved\r
+ UINT32 DIDL[8]; ///< Offset 32 Supported Display Devices ID List\r
+ UINT32 CPDL[8]; ///< Offset 64 Currently Attached Display Devices List\r
+ UINT32 CADL[8]; ///< Offset 96 Currently Active Display Devices List\r
+ UINT32 NADL[8]; ///< Offset 128 Next Active Devices List\r
+ UINT32 ASLP; ///< Offset 160 ASL Sleep Time Out\r
+ UINT32 TIDX; ///< Offset 164 Toggle Table Index\r
+ UINT32 CHPD; ///< Offset 168 Current Hotplug Enable Indicator\r
+ UINT32 CLID; ///< Offset 172 Current Lid State Indicator\r
+ UINT32 CDCK; ///< Offset 176 Current Docking State Indicator\r
+ UINT32 SXSW; ///< Offset 180 Display Switch Notification on Sx State Resume\r
+ UINT32 EVTS; ///< Offset 184 Events supported by ASL\r
+ UINT32 CNOT; ///< Offset 188 Current OS Notification\r
+ UINT32 NRDY; ///< Offset 192 Driver Status\r
+ UINT8 RSV3[0x3C]; ///< Offset 196 Reserved\r
+} INTEL_IGD_OPREGION_MBOX1;\r
+\r
+///\r
+/// OpRegion mailbox 2 (Software SCI Interface).\r
+///\r
+typedef struct {\r
+ UINT32 SCIC; ///< Offset 0 Software SCI Command / Status / Data\r
+ UINT32 PARM; ///< Offset 4 Software SCI Parameters\r
+ UINT32 DSLP; ///< Offset 8 Driver Sleep Time Out\r
+ UINT8 RSV4[0xF4]; ///< Offset 12 Reserved\r
+} INTEL_IGD_OPREGION_MBOX2;\r
+\r
+///\r
+/// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support).\r
+///\r
+typedef struct {\r
+ UINT32 ARDY; ///< Offset 0 Driver Readiness\r
+ UINT32 ASLC; ///< Offset 4 ASLE Interrupt Command / Status\r
+ UINT32 TCHE; ///< Offset 8 Technology Enabled Indicator\r
+ UINT32 ALSI; ///< Offset 12 Current ALS Luminance Reading\r
+ UINT32 BCLP; ///< Offset 16 Requested Backlight Britness\r
+ UINT32 PFIT; ///< Offset 20 Panel Fitting State or Request\r
+ UINT32 CBLV; ///< Offset 24 Current Brightness Level\r
+ UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Levels Duty Cycle Mapping Table\r
+ UINT32 CPFM; ///< Offset 68 Current Panel Fitting Mode\r
+ UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes\r
+ UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table & Identifier\r
+ UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness\r
+ UINT32 CCDV; ///< Offset 154 Color Correction Default Values\r
+ UINT8 RSV5[0x62]; ///< Offset 158 Reserved\r
+} INTEL_IGD_OPREGION_MBOX3;\r
+\r
+///\r
+/// OpRegion mailbox 4 (VBT).\r
+///\r
+typedef struct {\r
+ UINT8 RVBT[0x1C00]; ///< Offset 0 Raw VBT Data\r
+} INTEL_IGD_OPREGION_VBT;\r
+\r
+///\r
+/// IGD OpRegion Structure\r
+///\r
+typedef struct {\r
+ INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header\r
+ INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods\r
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