IGD OpRegion definition from Intel Integrated Graphics Device OpRegion\r
Specification.\r
\r
- https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf\r
-\r
- There are some mismatch between the specification and the implementation.\r
- The definition follows the latest implementation.\r
- 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]\r
- 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]\r
- 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]\r
- 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1C00]\r
+ https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r
\r
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
#ifndef _IGD_OPREGION_H_\r
#define _IGD_OPREGION_H_\r
\r
+#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"\r
+#define IGD_OPREGION_HEADER_MBOX1 BIT0\r
+#define IGD_OPREGION_HEADER_MBOX2 BIT1\r
+#define IGD_OPREGION_HEADER_MBOX3 BIT2\r
+#define IGD_OPREGION_HEADER_MBOX4 BIT3\r
+#define IGD_OPREGION_HEADER_MBOX5 BIT4\r
+\r
/**\r
- OpRegion structures:\r
- Sub-structures define the different parts of the OpRegion followed by the\r
- main structure representing the entire OpRegion.\r
+ OpRegion structures:\r
+ Sub-structures define the different parts of the OpRegion followed by the\r
+ main structure representing the entire OpRegion.\r
\r
- Note: These structures are packed to 1 byte offsets because the exact\r
- data location is requred by the supporting design specification due to\r
- the fact that the data is used by ASL and Graphics driver code compiled\r
- separatly.\r
+ @note: These structures are packed to 1 byte offsets because the exact\r
+ data location is required by the supporting design specification due to\r
+ the fact that the data is used by ASL and Graphics driver code compiled\r
+ separately.\r
**/\r
#pragma pack(1)\r
///\r
-/// OpRegion header (mailbox 0) structure and defines.\r
+/// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to\r
+/// identify a block of memory as the graphics driver OpRegion.\r
+/// Offset 0x0, Size 0x100\r
+///\r
+typedef struct {\r
+ CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature\r
+ UINT32 SIZE; ///< Offset 0x10 OpRegion Size\r
+ UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version\r
+ UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version\r
+ UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version\r
+ UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version\r
+ UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes\r
+ UINT32 DMOD; ///< Offset 0x5C Driver Model\r
+ UINT32 PCON; ///< Offset 0x60 Platform Configuration\r
+ CHAR16 DVER[0x10] ///< Offset 0x64 GOP Version\r
+ UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero\r
+} IGD_OPREGION_HEADER;\r
+\r
+///\r
+/// OpRegion Mailbox 1 - Public ACPI Methods\r
+/// Offset 0x100, Size 0x100\r
///\r
typedef struct {\r
- CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion Signature\r
- UINT32 SIZE; ///< Offset 16 OpRegion Size\r
- UINT32 OVER; ///< Offset 20 OpRegion Structure Version\r
- UINT8 SVER[0x20]; ///< Offset 24 System BIOS Build Version\r
- UINT8 VVER[0x10]; ///< Offset 56 Video BIOS Build Version\r
- UINT8 GVER[0x10]; ///< Offset 72 Graphic Driver Build Version\r
- UINT32 MBOX; ///< Offset 88 Supported Mailboxes\r
- UINT32 DMOD; ///< Offset 92 Driver Model\r
- UINT8 RSV1[0xA0]; ///< Offset 96 Reserved\r
-} INTEL_IGD_OPREGION_HEADER;\r
+ UINT32 DRDY; ///< Offset 0x100 Driver Readiness\r
+ UINT32 CSTS; ///< Offset 0x104 Status\r
+ UINT32 CEVT; ///< Offset 0x108 Current Event\r
+ UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero\r
+ UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List\r
+ UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List\r
+ UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List\r
+ UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List\r
+ UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out\r
+ UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index\r
+ UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator\r
+ UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator\r
+ UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator\r
+ UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on Sx State Resume\r
+ UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL\r
+ UINT32 CNOT; ///< Offset 0x1BC Current OS Notification\r
+ UINT32 NRDY; ///< Offset 0x1C0 Driver Status\r
+ UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)\r
+ UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List\r
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero\r
+} IGD_OPREGION_MBOX1;\r
\r
///\r
-/// OpRegion mailbox 1 (public ACPI Methods).\r
+/// OpRegion Mailbox 2 - Software SCI Interface\r
+/// Offset 0x200, Size 0x100\r
///\r
typedef struct {\r
- UINT32 DRDY; ///< Offset 0 Driver Readiness\r
- UINT32 CSTS; ///< Offset 4 Status\r
- UINT32 CEVT; ///< Offset 8 Current Event\r
- UINT8 RSV2[0x14]; ///< Offset 12 Reserved\r
- UINT32 DIDL[8]; ///< Offset 32 Supported Display Devices ID List\r
- UINT32 CPDL[8]; ///< Offset 64 Currently Attached Display Devices List\r
- UINT32 CADL[8]; ///< Offset 96 Currently Active Display Devices List\r
- UINT32 NADL[8]; ///< Offset 128 Next Active Devices List\r
- UINT32 ASLP; ///< Offset 160 ASL Sleep Time Out\r
- UINT32 TIDX; ///< Offset 164 Toggle Table Index\r
- UINT32 CHPD; ///< Offset 168 Current Hotplug Enable Indicator\r
- UINT32 CLID; ///< Offset 172 Current Lid State Indicator\r
- UINT32 CDCK; ///< Offset 176 Current Docking State Indicator\r
- UINT32 SXSW; ///< Offset 180 Display Switch Notification on Sx State Resume\r
- UINT32 EVTS; ///< Offset 184 Events supported by ASL\r
- UINT32 CNOT; ///< Offset 188 Current OS Notification\r
- UINT32 NRDY; ///< Offset 192 Driver Status\r
- UINT8 RSV3[0x3C]; ///< Offset 196 Reserved\r
-} INTEL_IGD_OPREGION_MBOX1;\r
+ UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data\r
+ UINT32 PARM; ///< Offset 0x204 Software SCI Parameters\r
+ UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out\r
+ UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero\r
+} IGD_OPREGION_MBOX2;\r
\r
///\r
-/// OpRegion mailbox 2 (Software SCI Interface).\r
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support\r
+/// Offset 0x300, Size 0x100\r
///\r
typedef struct {\r
- UINT32 SCIC; ///< Offset 0 Software SCI Command / Status / Data\r
- UINT32 PARM; ///< Offset 4 Software SCI Parameters\r
- UINT32 DSLP; ///< Offset 8 Driver Sleep Time Out\r
- UINT8 RSV4[0xF4]; ///< Offset 12 Reserved\r
-} INTEL_IGD_OPREGION_MBOX2;\r
+ UINT32 ARDY; ///< Offset 0x300 Driver Readiness\r
+ UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status\r
+ UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator\r
+ UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading\r
+ UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness\r
+ UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request\r
+ UINT32 CBLV; ///< Offset 0x318 Current Brightness Level\r
+ UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table\r
+ UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode\r
+ UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes\r
+ UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier\r
+ UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness\r
+ UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values\r
+ UINT32 PCFT; ///< Offset 0x39E Power Conservation Features\r
+ UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles\r
+ UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register\r
+ UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r
+ UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer\r
+ UINT32 STAT; ///< Offset 0x3B6 State Indicator\r
+ UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero\r
+} IGD_OPREGION_MBOX3;\r
\r
///\r
-/// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support).\r
+/// OpRegion Mailbox 4 - VBT Video BIOS Table\r
+/// Offset 0x400, Size 0x1800\r
///\r
typedef struct {\r
- UINT32 ARDY; ///< Offset 0 Driver Readiness\r
- UINT32 ASLC; ///< Offset 4 ASLE Interrupt Command / Status\r
- UINT32 TCHE; ///< Offset 8 Technology Enabled Indicator\r
- UINT32 ALSI; ///< Offset 12 Current ALS Luminance Reading\r
- UINT32 BCLP; ///< Offset 16 Requested Backlight Britness\r
- UINT32 PFIT; ///< Offset 20 Panel Fitting State or Request\r
- UINT32 CBLV; ///< Offset 24 Current Brightness Level\r
- UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Levels Duty Cycle Mapping Table\r
- UINT32 CPFM; ///< Offset 68 Current Panel Fitting Mode\r
- UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes\r
- UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table & Identifier\r
- UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness\r
- UINT32 CCDV; ///< Offset 154 Color Correction Default Values\r
- UINT8 RSV5[0x62]; ///< Offset 158 Reserved\r
-} INTEL_IGD_OPREGION_MBOX3;\r
+ UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data\r
+} IGD_OPREGION_MBOX4;\r
\r
///\r
-/// OpRegion mailbox 4 (VBT).\r
+/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync\r
+/// Offset 0x1C00, Size 0x400\r
///\r
typedef struct {\r
- UINT8 RVBT[0x1C00]; ///< Offset 0 Raw VBT Data\r
-} INTEL_IGD_OPREGION_VBT;\r
+ UINT32 PHED; ///< Offset 0x1C00 Panel Header\r
+ UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data)\r
+ UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero\r
+} IGD_OPREGION_MBOX5;\r
\r
///\r
/// IGD OpRegion Structure\r
///\r
typedef struct {\r
- INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header\r
- INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods\r
- INTEL_IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface\r
- INTEL_IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS/Driver Communication\r
- INTEL_IGD_OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data)\r
-} IGD_IGD_OPREGION_STRUCTURE;\r
+ IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)\r
+ IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)\r
+ IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)\r
+ IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)\r
+ IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)\r
+ IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)\r
+} IGD_OPREGION_STRUCTURE;\r
#pragma pack()\r
\r
#endif\r
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