+++ /dev/null
-/** @file\r
- The definition for VTD register.\r
- It is defined in "Intel VT for Direct IO Architecture Specification".\r
-\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef __VTD_REG_H__\r
-#define __VTD_REG_H__\r
-\r
-#pragma pack(1)\r
-\r
-//\r
-// Translation Structure Formats\r
-//\r
-#define VTD_ROOT_ENTRY_NUMBER 256\r
-#define VTD_CONTEXT_ENTRY_NUMBER 256\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Present:1;\r
- UINT32 Reserved_1:11;\r
- UINT32 ContextTablePointerLo:20;\r
- UINT32 ContextTablePointerHi:32;\r
-\r
- UINT64 Reserved_64;\r
- } Bits;\r
- struct {\r
- UINT64 Uint64Lo;\r
- UINT64 Uint64Hi;\r
- } Uint128;\r
-} VTD_ROOT_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 LowerPresent:1;\r
- UINT32 Reserved_1:11;\r
- UINT32 LowerContextTablePointerLo:20;\r
- UINT32 LowerContextTablePointerHi:32;\r
-\r
- UINT32 UpperPresent:1;\r
- UINT32 Reserved_65:11;\r
- UINT32 UpperContextTablePointerLo:20;\r
- UINT32 UpperContextTablePointerHi:32;\r
- } Bits;\r
- struct {\r
- UINT64 Uint64Lo;\r
- UINT64 Uint64Hi;\r
- } Uint128;\r
-} VTD_EXT_ROOT_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Present:1;\r
- UINT32 FaultProcessingDisable:1;\r
- UINT32 TranslationType:2;\r
- UINT32 Reserved_4:8;\r
- UINT32 SecondLevelPageTranslationPointerLo:20;\r
- UINT32 SecondLevelPageTranslationPointerHi:32;\r
-\r
- UINT32 AddressWidth:3;\r
- UINT32 Ignored_67:4;\r
- UINT32 Reserved_71:1;\r
- UINT32 DomainIdentifier:16;\r
- UINT32 Reserved_88:8;\r
- UINT32 Reserved_96:32;\r
- } Bits;\r
- struct {\r
- UINT64 Uint64Lo;\r
- UINT64 Uint64Hi;\r
- } Uint128;\r
-} VTD_CONTEXT_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Present:1;\r
- UINT32 FaultProcessingDisable:1;\r
- UINT32 TranslationType:3;\r
- UINT32 ExtendedMemoryType:3;\r
- UINT32 DeferredInvalidateEnable:1;\r
- UINT32 PageRequestEnable:1;\r
- UINT32 NestedTranslationEnable:1;\r
- UINT32 PASIDEnable:1;\r
- UINT32 SecondLevelPageTranslationPointerLo:20;\r
- UINT32 SecondLevelPageTranslationPointerHi:32;\r
-\r
- UINT32 AddressWidth:3;\r
- UINT32 PageGlobalEnable:1;\r
- UINT32 NoExecuteEnable:1;\r
- UINT32 WriteProtectEnable:1;\r
- UINT32 CacheDisable:1;\r
- UINT32 ExtendedMemoryTypeEnable:1;\r
- UINT32 DomainIdentifier:16;\r
- UINT32 SupervisorModeExecuteProtection:1;\r
- UINT32 ExtendedAccessedFlagEnable:1;\r
- UINT32 ExecuteRequestsEnable:1;\r
- UINT32 SecondLevelExecuteEnable:1;\r
- UINT32 Reserved_92:4;\r
- UINT32 PageAttributeTable0:3;\r
- UINT32 Reserved_Pat0:1;\r
- UINT32 PageAttributeTable1:3;\r
- UINT32 Reserved_Pat1:1;\r
- UINT32 PageAttributeTable2:3;\r
- UINT32 Reserved_Pat2:1;\r
- UINT32 PageAttributeTable3:3;\r
- UINT32 Reserved_Pat3:1;\r
- UINT32 PageAttributeTable4:3;\r
- UINT32 Reserved_Pat4:1;\r
- UINT32 PageAttributeTable5:3;\r
- UINT32 Reserved_Pat5:1;\r
- UINT32 PageAttributeTable6:3;\r
- UINT32 Reserved_Pat6:1;\r
- UINT32 PageAttributeTable7:3;\r
- UINT32 Reserved_Pat7:1;\r
-\r
- UINT32 PASIDTableSize:4;\r
- UINT32 Reserved_132:8;\r
- UINT32 PASIDTablePointerLo:20;\r
- UINT32 PASIDTablePointerHi:32;\r
-\r
- UINT32 Reserved_192:12;\r
- UINT32 PASIDStateTablePointerLo:20;\r
- UINT32 PASIDStateTablePointerHi:32;\r
- } Bits;\r
- struct {\r
- UINT64 Uint64_1;\r
- UINT64 Uint64_2;\r
- UINT64 Uint64_3;\r
- UINT64 Uint64_4;\r
- } Uint256;\r
-} VTD_EXT_CONTEXT_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Present:1;\r
- UINT32 Reserved_1:2;\r
- UINT32 PageLevelCacheDisable:1;\r
- UINT32 PageLevelWriteThrough:1;\r
- UINT32 Reserved_5:6;\r
- UINT32 SupervisorRequestsEnable:1;\r
- UINT32 FirstLevelPageTranslationPointerLo:20;\r
- UINT32 FirstLevelPageTranslationPointerHi:32;\r
- } Bits;\r
- UINT64 Uint64;\r
-} VTD_PASID_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Reserved_0:32;\r
- UINT32 ActiveReferenceCount:16;\r
- UINT32 Reserved_48:15;\r
- UINT32 DeferredInvalidate:1;\r
- } Bits;\r
- UINT64 Uint64;\r
-} VTD_PASID_STATE_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Present:1;\r
- UINT32 ReadWrite:1;\r
- UINT32 UserSupervisor:1;\r
- UINT32 PageLevelWriteThrough:1;\r
- UINT32 PageLevelCacheDisable:1;\r
- UINT32 Accessed:1;\r
- UINT32 Dirty:1;\r
- UINT32 PageSize:1; // It is PageAttribute:1 for 4K page entry\r
- UINT32 Global:1;\r
- UINT32 Ignored_9:1;\r
- UINT32 ExtendedAccessed:1;\r
- UINT32 Ignored_11:1;\r
- // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry\r
- UINT32 AddressLo:20;\r
- UINT32 AddressHi:20;\r
- UINT32 Ignored_52:11;\r
- UINT32 ExecuteDisable:1;\r
- } Bits;\r
- UINT64 Uint64;\r
-} VTD_FIRST_LEVEL_PAGING_ENTRY;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Read:1;\r
- UINT32 Write:1;\r
- UINT32 Execute:1;\r
- UINT32 ExtendedMemoryType:3;\r
- UINT32 IgnorePAT:1;\r
- UINT32 PageSize:1;\r
- UINT32 Ignored_8:3;\r
- UINT32 Snoop:1;\r
- UINT32 AddressLo:20;\r
- UINT32 AddressHi:20;\r
- UINT32 Ignored_52:10;\r
- UINT32 TransientMapping:1;\r
- UINT32 Ignored_63:1;\r
- } Bits;\r
- UINT64 Uint64;\r
-} VTD_SECOND_LEVEL_PAGING_ENTRY;\r
-\r
-//\r
-// Register Descriptions\r
-//\r
-#define R_VER_REG 0x00\r
-#define R_CAP_REG 0x08\r
-#define B_CAP_REG_RWBF BIT4\r
-#define R_ECAP_REG 0x10\r
-#define R_GCMD_REG 0x18\r
-#define B_GMCD_REG_WBF BIT27\r
-#define B_GMCD_REG_SRTP BIT30\r
-#define B_GMCD_REG_TE BIT31\r
-#define R_GSTS_REG 0x1C\r
-#define B_GSTS_REG_WBF BIT27\r
-#define B_GSTS_REG_RTPS BIT30\r
-#define B_GSTS_REG_TE BIT31\r
-#define R_RTADDR_REG 0x20\r
-#define R_CCMD_REG 0x28\r
-#define B_CCMD_REG_CIRG_MASK (BIT62|BIT61)\r
-#define V_CCMD_REG_CIRG_GLOBAL BIT61\r
-#define V_CCMD_REG_CIRG_DOMAIN BIT62\r
-#define V_CCMD_REG_CIRG_DEVICE (BIT62|BIT61)\r
-#define B_CCMD_REG_ICC BIT63\r
-#define R_FSTS_REG 0x34\r
-#define R_FECTL_REG 0x38\r
-#define R_FEDATA_REG 0x3C\r
-#define R_FEADDR_REG 0x40\r
-#define R_FEUADDR_REG 0x44\r
-#define R_AFLOG_REG 0x58\r
-\r
-#define R_IVA_REG 0x00 // + IRO\r
-#define B_IVA_REG_AM_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5)\r
-#define B_IVA_REG_AM_4K 0 // 1 page\r
-#define B_IVA_REG_AM_2M 9 // 2M page\r
-#define B_IVA_REG_IH BIT6\r
-#define R_IOTLB_REG 0x08 // + IRO\r
-#define B_IOTLB_REG_IIRG_MASK (BIT61|BIT60)\r
-#define V_IOTLB_REG_IIRG_GLOBAL BIT60\r
-#define V_IOTLB_REG_IIRG_DOMAIN BIT61\r
-#define V_IOTLB_REG_IIRG_PAGE (BIT61|BIT60)\r
-#define B_IOTLB_REG_IVT BIT63\r
-\r
-#define R_FRCD_REG 0x00 // + FRO\r
-\r
-#define R_PMEN_ENABLE_REG 0x64\r
-#define R_PMEN_LOW_BASE_REG 0x68\r
-#define R_PMEN_LOW_LIMITE_REG 0x6C\r
-#define R_PMEN_HIGH_BASE_REG 0x70\r
-#define R_PMEN_HIGH_LIMITE_REG 0x78\r
-\r
-typedef union {\r
- struct {\r
- UINT8 ND:3; // Number of domains supported\r
- UINT8 AFL:1; // Advanced Fault Logging\r
- UINT8 RWBF:1; // Required Write-Buffer Flushing\r
- UINT8 PLMR:1; // Protected Low-Memory Region\r
- UINT8 PHMR:1; // Protected High-Memory Region\r
- UINT8 CM:1; // Caching Mode\r
-\r
- UINT8 SAGAW:5; // Supported Adjusted Guest Address Widths\r
- UINT8 Rsvd_13:3;\r
-\r
- UINT8 MGAW:6; // Maximum Guest Address Width\r
- UINT8 ZLR:1; // Zero Length Read\r
- UINT8 Rsvd_23:1;\r
-\r
- UINT16 FRO:10; // Fault-recording Register offset\r
- UINT16 SLLPS:4; // Second Level Large Page Support\r
- UINT16 Rsvd_38:1;\r
- UINT16 PSI:1; // Page Selective Invalidation\r
-\r
- UINT8 NFR:8; // Number of Fault-recording Registers\r
-\r
- UINT8 MAMV:6; // Maximum Address Mask Value\r
- UINT8 DWD:1; // Write Draining\r
- UINT8 DRD:1; // Read Draining\r
-\r
- UINT8 FL1GP:1; // First Level 1-GByte Page Support\r
- UINT8 Rsvd_57:2;\r
- UINT8 PI:1; // Posted Interrupts Support\r
- UINT8 Rsvd_60:4;\r
- } Bits;\r
- UINT64 Uint64;\r
-} VTD_CAP_REG;\r
-\r
-typedef union {\r
- struct {\r
- UINT8 C:1; // Page-walk Coherency\r
- UINT8 QI:1; // Queued Invalidation support\r
- UINT8 DT:1; // Device-TLB support\r
- UINT8 IR:1; // Interrupt Remapping support\r
- UINT8 EIM:1; // Extended Interrupt Mode\r
- UINT8 Rsvd_5:1;\r
- UINT8 PT:1; // Pass Through\r
- UINT8 SC:1; // Snoop Control\r
-\r
- UINT16 IRO:10; // IOTLB Register Offset\r
- UINT16 Rsvd_18:2;\r
- UINT16 MHMV:4; // Maximum Handle Mask Value\r
-\r
- UINT8 ECS:1; // Extended Context Support\r
- UINT8 MTS:1; // Memory Type Support\r
- UINT8 NEST:1; // Nested Translation Support\r
- UINT8 DIS:1; // Deferred Invalidate Support\r
- UINT8 PASID:1; // Process Address Space ID Support\r
- UINT8 PRS:1; // Page Request Support\r
- UINT8 ERS:1; // Execute Request Support\r
- UINT8 SRS:1; // Supervisor Request Support\r
-\r
- UINT32 Rsvd_32:1;\r
- UINT32 NWFS:1; // No Write Flag Support\r
- UINT32 EAFS:1; // Extended Accessed Flag Support\r
- UINT32 PSS:5; // PASID Size Supported\r
- UINT32 Rsvd_40:24;\r
- } Bits;\r
- UINT64 Uint64;\r
-} VTD_ECAP_REG;\r
-\r
-typedef union {\r
- struct {\r
- UINT32 Rsvd_0:12;\r
- UINT32 FILo:20; // FaultInfo\r
- UINT32 FIHi:32; // FaultInfo\r
-\r
- UINT32 SID:16; // Source Identifier\r
- UINT32 Rsvd_80:13;\r
- UINT32 PRIV:1; // Privilege Mode Requested\r
- UINT32 EXE:1; // Execute Permission Requested\r
- UINT32 PP:1; // PASID Present\r
-\r
- UINT32 FR:8; // Fault Reason\r
- UINT32 PV:20; // PASID Value\r
- UINT32 AT:2; // Address Type\r
- UINT32 T:1; // Type (0: Write, 1: Read)\r
- UINT32 F:1; // Fault\r
- } Bits;\r
- UINT64 Uint64[2];\r
-} VTD_FRCD_REG;\r
-\r
-typedef union {\r
- struct {\r
- UINT8 Function:3;\r
- UINT8 Device:5;\r
- UINT8 Bus;\r
- } Bits;\r
- struct {\r
- UINT8 ContextIndex;\r
- UINT8 RootIndex;\r
- } Index;\r
- UINT16 Uint16;\r
-} VTD_SOURCE_ID;\r
-\r
-#pragma pack()\r
-\r
-#endif\r
-\r
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