IntelSiliconPkg/VTdDxe: Disable PMR

[mirror_edk2.git] / IntelSiliconPkg / IntelVTdDxe / VtdReg.c

diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
index 7402d818761017a90a4703c225e9793d67f0d4ad..1404af7cd7817fb4163b9eb01e7ad2df66631d87 100644 (file)
--- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
+++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
@@ -195,6 +195,39 @@ PrepareVtdConfig (
   return ;\r
 }\r
 \r
+/**\r
+  Disable PMR in all VTd engine.\r
+**/\r
+VOID\r
+DisablePmr (\r
+  VOID\r
+  )\r
+{\r
+  UINT32        Reg32;\r
+  VTD_CAP_REG   CapReg;\r
+  UINTN         Index;\r
+\r
+  DEBUG ((DEBUG_INFO,"DisablePmr\n"));\r
+  for (Index = 0; Index < mVtdUnitNumber; Index++) {\r
+    CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);\r
+    if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {\r
+      continue ;\r
+    }\r
+\r
+    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);\r
+    if ((Reg32 & BIT0) != 0) {\r
+      MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0);\r
+      do {\r
+        Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);\r
+      } while((Reg32 & BIT0) != 0);\r
+      DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));\r
+    } else {\r
+      DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));\r
+    }\r
+  }\r
+  return ;\r
+}\r
+\r
 /**\r
   Enable DMAR translation.\r
 \r
@@ -259,6 +292,11 @@ EnableDmar (
     DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));\r
   }\r
 \r
+  //\r
+  // Need disable PMR, since we already setup translation table.\r
+  //\r
+  DisablePmr ();\r
+\r
   mVtdEnabled = TRUE;\r
 \r
   return EFI_SUCCESS;\r
@@ -502,7 +540,7 @@ DumpVtdIfError (
     for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {\r
       FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));\r
       FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));\r
-      if ((FrcdReg.Uint64[0] != 0) || (FrcdReg.Uint64[1] != 0)) {\r
+      if (FrcdReg.Bits.F != 0) {\r
         HasError = TRUE;\r
       }\r
     }\r
@@ -511,6 +549,17 @@ DumpVtdIfError (
       DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));\r
       DumpVtdRegs (Num);\r
       DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));\r
+      //\r
+      // Clear\r
+      //\r
+      for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {\r
+        FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));\r
+        if (FrcdReg.Bits.F != 0) {\r
+          FrcdReg.Bits.F = 0;\r
+          MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.Uint64[1]);\r
+        }\r
+        MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));\r
+      }\r
     }\r
   }\r
 }\r