/** @file\r
The file for AHCI mode of ATA host controller.\r
\r
- Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
in the Status Register, the Error Register's value is also be dumped.\r
\r
@param PciIo The PCI IO protocol instance.\r
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
\r
EFIAPI\r
AhciDumpPortStatus (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_AHCI_REGISTERS *AhciRegisters,\r
IN UINT8 Port,\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
)\r
{\r
- UINT32 Offset;\r
+ UINTN Offset;\r
UINT32 Data;\r
+ UINTN FisBaseAddr;\r
+ EFI_STATUS Status;\r
\r
ASSERT (PciIo != NULL);\r
\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
- Data = AhciReadReg (PciIo, Offset);\r
-\r
if (AtaStatusBlock != NULL) {\r
ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));\r
\r
- AtaStatusBlock->AtaStatus = (UINT8)Data;\r
- if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {\r
- AtaStatusBlock->AtaError = (UINT8)(Data >> 8);\r
+ FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
+\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // If D2H FIS is received, update StatusBlock with its content.\r
+ //\r
+ CopyMem (AtaStatusBlock, (UINT8 *)Offset, sizeof (EFI_ATA_STATUS_BLOCK));\r
+ } else {\r
+ //\r
+ // If D2H FIS is not received, only update Status & Error field through PxTFD\r
+ // as there is no other way to get the content of the Shadow Register Block.\r
+ //\r
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
+ Data = AhciReadReg (PciIo, (UINT32)Offset);\r
+\r
+ AtaStatusBlock->AtaStatus = (UINT8)Data;\r
+ if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {\r
+ AtaStatusBlock->AtaError = (UINT8)(Data >> 8);\r
+ }\r
}\r
}\r
}\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
\r
- return AhciWaitMmioSet (\r
- PciIo,\r
- Offset,\r
- EFI_AHCI_PORT_CMD_FR,\r
- EFI_AHCI_PORT_CMD_FR,\r
- Timeout\r
- );\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
Map\r
);\r
\r
- AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);\r
+ AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);\r
\r
return Status;\r
}\r
}\r
}\r
\r
- AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);\r
+ AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);\r
return Status;\r
}\r
\r
Timeout\r
);\r
\r
- AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);\r
+ AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);\r
\r
return Status;\r
}\r
//\r
// Setting the command\r
//\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SACT;\r
- AhciAndReg (PciIo, Offset, 0);\r
- AhciOrReg (PciIo, Offset, CmdSlotBit);\r
-\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;\r
AhciAndReg (PciIo, Offset, 0);\r
AhciOrReg (PciIo, Offset, CmdSlotBit);\r
);\r
\r
if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "Port %d COMRESET failed: %r\n", Port, Status));\r
return Status;\r
}\r
\r
UINT64 Delay;\r
UINT32 Value;\r
\r
- AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
+ //\r
+ // Make sure that GHC.AE bit is set before accessing any AHCI registers.\r
+ //\r
+ Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
+\r
+ if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {\r
+ AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
+ }\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);\r
\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
- @param PortMultiplier The timeout value of stop.\r
+ @param PortMultiplier The port multiplier port number.\r
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
\r
@retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
- @param PortMultiplier The timeout value of stop.\r
+ @param PortMultiplier The port multiplier port number.\r
@param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.\r
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
- @param PortMultiplier The timeout value of stop.\r
+ @param PortMultiplier The port multiplier port number.\r
@param Buffer The data buffer to store IDENTIFY PACKET data.\r
\r
@retval EFI_DEVICE_ERROR The cmd abort with error occurs.\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
- @param PortMultiplier The timeout value of stop.\r
+ @param PortMultiplier The port multiplier port number.\r
@param Buffer The data buffer to store IDENTIFY PACKET data.\r
\r
@retval EFI_DEVICE_ERROR The cmd abort with error occurs.\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
@param Port The number of port.\r
- @param PortMultiplier The timeout value of stop.\r
+ @param PortMultiplier The port multiplier port number.\r
@param Feature The data to send Feature register.\r
@param FeatureSpecificData The specific data for SET FEATURE cmd.\r
\r
EFI_ATA_COLLECTIVE_MODE *SupportedModes;\r
EFI_ATA_TRANSFER_MODE TransferMode;\r
UINT32 PhyDetectDelay;\r
+ UINT32 Value;\r
\r
if (Instance == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
- // Enable AE before accessing any AHCI registers\r
+ // Collect AHCI controller information\r
//\r
- AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
+ Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);\r
\r
//\r
- // Collect AHCI controller information\r
+ // Make sure that GHC.AE bit is set before accessing any AHCI registers.\r
//\r
- Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);\r
+ Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
+\r
+ if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {\r
+ AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
+ }\r
+\r
+ //\r
+ // Enable 64-bit DMA support in the PCI layer if this controller\r
+ // supports it.\r
+ //\r
+ if ((Capability & EFI_AHCI_CAP_S64A) != 0) {\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,\r
+ NULL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_WARN,\r
+ "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",\r
+ Status));\r
+ }\r
+ }\r
\r
//\r
// Get the number of command slots per port supported by this HBA.\r
//\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
- Status = AhciWaitMmioSet (\r
- PciIo,\r
- Offset,\r
- EFI_AHCI_PORT_CMD_FR,\r
- EFI_AHCI_PORT_CMD_FR,\r
- EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT\r
- );\r
- if (EFI_ERROR (Status)) {\r
- continue;\r
- }\r
\r
//\r
// Wait no longer than 10 ms to wait the Phy to detect the presence of a device.\r
} while (PhyDetectDelay > 0);\r
\r
if (PhyDetectDelay == 0) {\r
+ DEBUG ((EFI_D_ERROR, "Port %d Device presence detected but phy not ready (TFD=0x%X)\n", Port, Data));\r
continue;\r
}\r
\r
//\r
// Found a ATA or ATAPI device, add it into the device list.\r
//\r
- CreateNewDeviceInfo (Instance, Port, 0, DeviceType, &Buffer);\r
+ CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);\r
if (DeviceType == EfiIdeHarddisk) {\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));\r
}\r
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