UINT64 MaxReceiveFisSize;\r
UINT64 MaxCommandListSize;\r
UINT64 MaxCommandTableSize;\r
+ EFI_PHYSICAL_ADDRESS AhciRFisPciAddr;\r
+ EFI_PHYSICAL_ADDRESS AhciCmdListPciAddr;\r
+ EFI_PHYSICAL_ADDRESS AhciCommandTablePciAddr;\r
\r
Buffer = NULL;\r
//\r
PciIo,\r
AllocateAnyPages,\r
EfiBootServicesData,\r
- (UINTN)EFI_SIZE_TO_PAGES (MaxReceiveFisSize),\r
+ EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),\r
&Buffer,\r
0\r
);\r
EfiPciIoOperationBusMasterCommonBuffer,\r
Buffer,\r
&Bytes,\r
- (EFI_PHYSICAL_ADDRESS *) &AhciRegisters->AhciRFisPciAddr,\r
+ &AhciRFisPciAddr,\r
&AhciRegisters->MapRFis\r
);\r
\r
goto Error6;\r
}\r
\r
- if ((!Support64Bit) && ((EFI_PHYSICAL_ADDRESS)(UINTN)AhciRegisters->AhciRFisPciAddr > 0x100000000ULL)) {\r
+ if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {\r
//\r
// The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.\r
//\r
Status = EFI_DEVICE_ERROR;\r
goto Error5;\r
}\r
+ AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;\r
\r
//\r
// Allocate memory for command list\r
PciIo,\r
AllocateAnyPages,\r
EfiBootServicesData,\r
- (UINTN)EFI_SIZE_TO_PAGES (MaxCommandListSize),\r
+ EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),\r
&Buffer,\r
0\r
);\r
EfiPciIoOperationBusMasterCommonBuffer,\r
Buffer,\r
&Bytes,\r
- (EFI_PHYSICAL_ADDRESS *)&AhciRegisters->AhciCmdListPciAddr,\r
+ &AhciCmdListPciAddr,\r
&AhciRegisters->MapCmdList\r
);\r
\r
goto Error4;\r
}\r
\r
- if ((!Support64Bit) && ((EFI_PHYSICAL_ADDRESS)(UINTN)AhciRegisters->AhciCmdListPciAddr > 0x100000000ULL)) {\r
+ if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {\r
//\r
// The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.\r
//\r
Status = EFI_DEVICE_ERROR;\r
goto Error3;\r
}\r
+ AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;\r
\r
//\r
// Allocate memory for command table\r
PciIo,\r
AllocateAnyPages,\r
EfiBootServicesData,\r
- (UINTN)EFI_SIZE_TO_PAGES (MaxCommandTableSize),\r
+ EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),\r
&Buffer,\r
0\r
);\r
EfiPciIoOperationBusMasterCommonBuffer,\r
Buffer,\r
&Bytes,\r
- (EFI_PHYSICAL_ADDRESS *)&AhciRegisters->AhciCommandTablePciAddr,\r
+ &AhciCommandTablePciAddr,\r
&AhciRegisters->MapCommandTable\r
);\r
\r
goto Error2;\r
}\r
\r
- if ((!Support64Bit) && ((EFI_PHYSICAL_ADDRESS)(UINTN)AhciRegisters->AhciCommandTablePciAddr > 0x100000000ULL)) {\r
+ if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {\r
//\r
// The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.\r
//\r
Status = EFI_DEVICE_ERROR;\r
goto Error1;\r
}\r
+ AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;\r
\r
return EFI_SUCCESS;\r
//\r
Error2:\r
PciIo->FreeBuffer (\r
PciIo,\r
- (UINTN)EFI_SIZE_TO_PAGES (MaxCommandTableSize),\r
+ EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),\r
AhciRegisters->AhciCommandTable\r
);\r
Error3:\r
Error4:\r
PciIo->FreeBuffer (\r
PciIo,\r
- (UINTN)EFI_SIZE_TO_PAGES (MaxCommandListSize),\r
+ EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),\r
AhciRegisters->AhciCmdList\r
);\r
Error5:\r
Error6:\r
PciIo->FreeBuffer (\r
PciIo,\r
- (UINTN)EFI_SIZE_TO_PAGES (MaxReceiveFisSize),\r
+ EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),\r
AhciRegisters->AhciRFis\r
);\r
\r