UINT16 DeviceControl; /* when write */\r
} IDE_AltStatus_OR_DeviceControl;\r
\r
+\r
+typedef enum {\r
+ IdePrimary = 0,\r
+ IdeSecondary = 1,\r
+ IdeMaxChannel = 2\r
+} EFI_IDE_CHANNEL;\r
+\r
+///\r
+\r
+\r
+//\r
+// Bit definitions in Programming Interface byte of the Class Code field\r
+// in PCI IDE controller's Configuration Space\r
+//\r
+#define IDE_PRIMARY_OPERATING_MODE BIT0\r
+#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1\r
+#define IDE_SECONDARY_OPERATING_MODE BIT2\r
+#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3\r
+\r
+\r
+#define ATAPI_MAX_CHANNEL 2\r
+\r
///\r
/// IDE registers set\r
///\r
UINT16 CylinderMsb;\r
UINT16 Head;\r
IDE_CMD_OR_STATUS Reg;\r
-\r
IDE_AltStatus_OR_DeviceControl Alt;\r
UINT16 DriveAddress;\r
-\r
- UINT16 MasterSlave;\r
} IDE_BASE_REGISTERS;\r
\r
#define ATAPI_SCSI_PASS_THRU_DEV_SIGNATURE EFI_SIGNATURE_32 ('a', 's', 'p', 't')\r
\r
typedef struct {\r
- UINTN Signature;\r
-\r
- EFI_HANDLE Handle;\r
- EFI_SCSI_PASS_THRU_PROTOCOL ScsiPassThru;\r
- EFI_SCSI_PASS_THRU_MODE ScsiPassThruMode;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
-\r
+ UINTN Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_SCSI_PASS_THRU_PROTOCOL ScsiPassThru;\r
+ EFI_SCSI_PASS_THRU_MODE ScsiPassThruMode;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
//\r
// Local Data goes here\r
//\r
- IDE_BASE_REGISTERS *IoPort;\r
-\r
- CHAR16 ControllerName[100];\r
- CHAR16 ChannelName[100];\r
-\r
- UINT32 LatestTargetId;\r
- UINT64 LatestLun;\r
-\r
+ IDE_BASE_REGISTERS *IoPort;\r
+ IDE_BASE_REGISTERS AtapiIoPortRegisters[2];\r
+ CHAR16 ControllerName[100];\r
+ CHAR16 ChannelName[100];\r
+ UINT32 LatestTargetId;\r
+ UINT64 LatestLun;\r
} ATAPI_SCSI_PASS_THRU_DEV;\r
\r
+//\r
+// IDE registers' base addresses\r
+//\r
+typedef struct {\r
+ UINT16 CommandBlockBaseAddr;\r
+ UINT16 ControlBlockBaseAddr;\r
+} IDE_REGISTERS_BASE_ADDR;\r
+\r
#define ATAPI_SCSI_PASS_THRU_DEV_FROM_THIS(a) \\r
CR (a, \\r
ATAPI_SCSI_PASS_THRU_DEV, \\r
ATAPI_SCSI_PASS_THRU_DEV *AtapiScsiPrivate\r
)\r
;\r
+EFI_STATUS\r
+GetIdeRegistersBaseAddr (\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ OUT IDE_REGISTERS_BASE_ADDR *IdeRegsBaseAddr\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Get IDE IO port registers' base addresses by mode. In 'Compatibility' mode,\r
+ use fixed addresses. In Native-PCI mode, get base addresses from BARs in\r
+ the PCI IDE controller's Configuration Space.\r
+\r
+Arguments:\r
+ PciIo - Pointer to the EFI_PCI_IO_PROTOCOL instance\r
+ IdeRegsBaseAddr - Pointer to IDE_REGISTERS_BASE_ADDR to \r
+ receive IDE IO port registers' base addresses\r
+ \r
+Returns:\r
+\r
+ EFI_STATUS\r
+ \r
+--*/\r
+;\r
+\r
+VOID\r
+InitAtapiIoPortRegisters (\r
+ IN ATAPI_SCSI_PASS_THRU_DEV *AtapiScsiPrivate,\r
+ IN IDE_REGISTERS_BASE_ADDR *IdeRegsBaseAddr\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initialize each Channel's Base Address of CommandBlock and ControlBlock.\r
+\r
+Arguments:\r
+ \r
+ AtapiScsiPrivate - The pointer of ATAPI_SCSI_PASS_THRU_DEV\r
+ IdeRegsBaseAddr - The pointer of IDE_REGISTERS_BASE_ADDR\r
+ \r
+Returns:\r
+ \r
+ None\r
+\r
+--*/ \r
+;\r
+\r
#endif\r