MdeModulePkg/EhciDxe: Update async polling interval to 1ms.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / Ehci.h

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
index 4327f2368a3f4054ef50684b24bec7a469b848d5..7177658092c302ebd03a28ebcb2d3362664eb89b 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h
@@ -2,7 +2,7 @@
 \r
   Provides some data struct used by EHCI controller driver.\r
 \r
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -66,10 +66,10 @@ typedef struct _USB2_HC_DEV  USB2_HC_DEV;
 \r
 //\r
 // Sync and Async transfer polling interval, set by experience,\r
-// and the unit of Async is 100us, means 50ms as interval.\r
+// and the unit of Async is 100us, means 1ms as interval.\r
 //\r
 #define EHC_SYNC_POLL_INTERVAL       (1 * EHC_1_MILLISECOND)\r
-#define EHC_ASYNC_POLL_INTERVAL      (50 * 10000U)\r
+#define EHC_ASYNC_POLL_INTERVAL      EFI_TIMER_PERIOD_MILLISECONDS(1)\r
 \r
 //\r
 // EHCI debug port control status register bit definition\r