/** @file\r
PCI eunmeration implementation on entire PCI bus system for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
//\r
// Notify the pci bus enumeration is about to begin\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// Start the bus allocation phase\r
//\r
// Notify the pci bus enumeration is about to complete\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
//\r
// Process P2C\r
{\r
EFI_STATUS Status;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;\r
UINT8 SubBusNumber;\r
UINT8 StartBusNumber;\r
UINT8 PaddedBusRange;\r
EFI_HANDLE RootBridgeHandle;\r
+ UINT8 Desc;\r
+ UINT64 AddrLen;\r
+ UINT64 AddrRangeMin;\r
\r
SubBusNumber = 0;\r
StartBusNumber = 0;\r
\r
REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_BUS_ENUM,\r
+ EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,\r
RootBridgeDev->DevicePath\r
);\r
\r
return Status;\r
}\r
\r
+ if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ RootBridgeDev->BusNumberRanges = Configuration;\r
+\r
+ //\r
+ // Sort the descriptors in ascending order\r
+ //\r
+ for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {\r
+ Configuration2 = Configuration1;\r
+ for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {\r
+ if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {\r
+ Configuration2 = Configuration3;\r
+ }\r
+ }\r
+ //\r
+ // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,\r
+ // so only need to swap these two fields.\r
+ //\r
+ if (Configuration2 != Configuration1) {\r
+ AddrRangeMin = Configuration1->AddrRangeMin;\r
+ Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;\r
+ Configuration2->AddrRangeMin = AddrRangeMin;\r
+ \r
+ AddrLen = Configuration1->AddrLen;\r
+ Configuration1->AddrLen = Configuration2->AddrLen;\r
+ Configuration2->AddrLen = AddrLen;\r
+ }\r
+ }\r
+\r
//\r
// Get the bus number to start with\r
//\r
StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
- PaddedBusRange = (UINT8) (Configuration->AddrRangeMax);\r
\r
//\r
// Initialize the subordinate bus number\r
//\r
Status = PciScanBus (\r
RootBridgeDev,\r
- (UINT8) (Configuration->AddrRangeMin),\r
+ StartBusNumber,\r
&SubBusNumber,\r
&PaddedBusRange\r
);\r
//\r
// Assign max bus number scanned\r
//\r
- Configuration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
+\r
+ Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ } \r
+\r
+ //\r
+ // Find the bus range which contains the higest bus number, then returns the number of buses\r
+ // that should be decoded.\r
+ //\r
+ while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {\r
+ Configuration++;\r
+ }\r
+ AddrLen = Configuration->AddrLen;\r
+ Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;\r
\r
+ //\r
+ // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.\r
+ //\r
+ Configuration++;\r
+ Desc = Configuration->Desc;\r
+ Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ \r
//\r
// Set bus number\r
//\r
Status = PciResAlloc->SetBusNumbers (\r
PciResAlloc,\r
RootBridgeHandle,\r
- Configuration\r
+ RootBridgeDev->BusNumberRanges\r
);\r
\r
- FreePool (Configuration);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ //\r
+ // Restore changed fields\r
+ //\r
+ Configuration->Desc = Desc;\r
+ (Configuration - 1)->AddrLen = AddrLen;\r
+ \r
+ return Status;\r
}\r
\r
/**\r
//\r
// Reserved one bus for cardbus bridge\r
//\r
- SecondBus = ++(*SubBusNumber);\r
+ Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ SecondBus = *SubBusNumber;\r
\r
Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
\r
if (Temp == PciDevice) {\r
InitializePciDevice (Temp);\r
RemoveEntryList (CurrentLink);\r
- FreePciDevice (Temp);\r
return EFI_SUCCESS;\r
}\r
\r
//\r
Status = RejectPciDevice (PciResNode->PciDev);\r
if (Status == EFI_SUCCESS) {\r
+ DEBUG ((\r
+ EFI_D_ERROR,\r
+ "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",\r
+ PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber\r
+ ));\r
\r
//\r
// Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
);\r
}\r
\r
- return EFI_SUCCESS;\r
+ return Status;\r
}\r
\r
/**\r
RootBridgeHandle = Temp->Handle;\r
\r
if (Operation == EfiPciHotPlugRequestAdd) {\r
+ //\r
+ // Report Status Code to indicate hot plug happens\r
+ //\r
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),\r
+ Temp->DevicePath\r
+ );\r
\r
if (NumberOfChildren != NULL) {\r
*NumberOfChildren = 0;\r
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