/** @file\r
EFI PCI IO protocol functions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PciBus.h"\r
\r
+extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;\r
+\r
//\r
// Pci Io Protocol Interface\r
//\r
OUT VOID **Mapping\r
)\r
{\r
- EFI_STATUS Status;\r
- PCI_IO_DEVICE *PciIoDevice;\r
+ EFI_STATUS Status;\r
+ PCI_IO_DEVICE *PciIoDevice;\r
+ UINT64 IoMmuAttribute;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION RootBridgeIoOperation;\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+ RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;\r
if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {\r
- Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);\r
+ RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);\r
}\r
\r
Status = PciIoDevice->PciRootBridgeIo->Map (\r
PciIoDevice->PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,\r
+ RootBridgeIoOperation,\r
HostAddress,\r
NumberOfBytes,\r
DeviceAddress,\r
);\r
}\r
\r
+ if (mIoMmuProtocol != NULL) {\r
+ if (!EFI_ERROR (Status)) {\r
+ switch (Operation) {\r
+ case EfiPciIoOperationBusMasterRead:\r
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;\r
+ break;\r
+ case EfiPciIoOperationBusMasterWrite:\r
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;\r
+ break;\r
+ case EfiPciIoOperationBusMasterCommonBuffer:\r
+ IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;\r
+ break;\r
+ default:\r
+ ASSERT(FALSE);\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ mIoMmuProtocol->SetAttribute (\r
+ mIoMmuProtocol,\r
+ PciIoDevice->Handle,\r
+ *Mapping,\r
+ IoMmuAttribute\r
+ );\r
+ }\r
+ }\r
+\r
return Status;\r
}\r
\r
\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
\r
+ if (mIoMmuProtocol != NULL) {\r
+ mIoMmuProtocol->SetAttribute (\r
+ mIoMmuProtocol,\r
+ PciIoDevice->Handle,\r
+ Mapping,\r
+ 0\r
+ );\r
+ }\r
+\r
Status = PciIoDevice->PciRootBridgeIo->Unmap (\r
PciIoDevice->PciRootBridgeIo,\r
Mapping\r
\r
/**\r
Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
- mapping.\r
+ or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
@param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
@param Type This parameter is not used and must be ignored.\r
\r
@retval EFI_SUCCESS The requested memory pages were allocated.\r
@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
- MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
+ MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
\r
return Status;\r
}\r
\r
+/**\r
+ Retrieve the AddrTranslationOffset from RootBridgeIo for the\r
+ specified range.\r
+\r
+ @param RootBridgeIo Root Bridge IO instance.\r
+ @param AddrRangeMin The base address of the MMIO.\r
+ @param AddrLen The length of the MMIO.\r
+\r
+ @retval The AddrTranslationOffset from RootBridgeIo for the \r
+ specified range, or (UINT64) -1 if the range is not\r
+ found in RootBridgeIo.\r
+**/\r
+UINT64\r
+GetMmioAddressTranslationOffset (\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,\r
+ UINT64 AddrRangeMin,\r
+ UINT64 AddrLen\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
+\r
+ Status = RootBridgeIo->Configuration (\r
+ RootBridgeIo,\r
+ (VOID **) &Configuration\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return (UINT64) -1;\r
+ }\r
+\r
+ // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration()\r
+ // returns host address instead of device address, while AddrTranslationOffset\r
+ // is not zero, and device address = host address + AddrTranslationOffset, so\r
+ // we convert host address to device address for range compare.\r
+ while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
+ if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&\r
+ (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) &&\r
+ (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen)\r
+ ) {\r
+ return Configuration->AddrTranslationOffset;\r
+ }\r
+ Configuration++;\r
+ }\r
+\r
+ //\r
+ // The resource occupied by BAR should be in the range reported by RootBridge.\r
+ //\r
+ ASSERT (FALSE);\r
+ return (UINT64) -1;\r
+}\r
+\r
/**\r
Gets the attributes that this PCI controller supports setting on a BAR using\r
SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
base address for resource range. The legal range for this field is 0..5.\r
@param Supports A pointer to the mask of attributes that this PCI controller supports\r
setting for this BAR with SetBarAttributes().\r
- @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
+ @param Resources A pointer to the resource descriptors that describe the current\r
configuration of this BAR of the PCI controller.\r
\r
@retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
controller supports are returned in Supports. If Resources\r
- is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
+ is not NULL, then the resource descriptors that the PCI\r
controller is currently using are returned in Resources.\r
@retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
@retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
break;\r
\r
- case PciBarTypeMem32:\r
+ case PciBarTypePMem32:\r
//\r
- // Mem\r
+ // prefechable\r
//\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
//\r
- // 32 bit\r
+ // Fall through\r
//\r
- Descriptor->AddrSpaceGranularity = 32;\r
- break;\r
-\r
- case PciBarTypePMem32:\r
+ case PciBarTypeMem32:\r
//\r
// Mem\r
//\r
Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
//\r
- // prefechable\r
- //\r
- Descriptor->SpecificFlag = 0x6;\r
- //\r
// 32 bit\r
//\r
Descriptor->AddrSpaceGranularity = 32;\r
break;\r
\r
- case PciBarTypeMem64:\r
+ case PciBarTypePMem64:\r
//\r
- // Mem\r
+ // prefechable\r
//\r
- Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r
//\r
- // 64 bit\r
+ // Fall through\r
//\r
- Descriptor->AddrSpaceGranularity = 64;\r
- break;\r
-\r
- case PciBarTypePMem64:\r
+ case PciBarTypeMem64:\r
//\r
// Mem\r
//\r
Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
//\r
- // prefechable\r
- //\r
- Descriptor->SpecificFlag = 0x6;\r
- //\r
// 64 bit\r
//\r
Descriptor->AddrSpaceGranularity = 64;\r
End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);\r
End->Desc = ACPI_END_TAG_DESCRIPTOR;\r
End->Checksum = 0;\r
+\r
+ //\r
+ // Get the Address Translation Offset\r
+ //\r
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
+ Descriptor->AddrTranslationOffset = GetMmioAddressTranslationOffset (\r
+ PciIoDevice->PciRootBridgeIo,\r
+ Descriptor->AddrRangeMin,\r
+ Descriptor->AddrLen\r
+ );\r
+ if (Descriptor->AddrTranslationOffset == (UINT64) -1) {\r
+ FreePool (Descriptor);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ }\r
+\r
+ // According to UEFI spec 2.7, we need return host address for\r
+ // PciIo->GetBarAttributes, and host address = device address - translation.\r
+ Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset;\r
}\r
\r
return EFI_SUCCESS;\r
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