/** @file\r
Internal library implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PciBus.h"\r
\r
+GLOBAL_REMOVE_IF_UNREFERENCED\r
+CHAR16 *mBarTypeStr[] = {\r
+ L"Unknow",\r
+ L" Io16",\r
+ L" Io32",\r
+ L" Mem32",\r
+ L"PMem32",\r
+ L" Mem64",\r
+ L"PMem64",\r
+ L" Io",\r
+ L" Mem",\r
+ L"Unknow"\r
+ };\r
\r
/**\r
Retrieve the PCI Card device BAR information via PciIo interface.\r
}\r
}\r
\r
+/**\r
+ Dump the resourc map of the bridge device.\r
+\r
+ @param[in] BridgeResource Resource descriptor of the bridge device.\r
+**/\r
+VOID\r
+DumpBridgeResource (\r
+ IN PCI_RESOURCE_NODE *BridgeResource\r
+ )\r
+{\r
+ LIST_ENTRY *Link;\r
+ PCI_RESOURCE_NODE *Resource;\r
+ PCI_BAR *Bar;\r
+\r
+ if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {\r
+ DEBUG ((\r
+ EFI_D_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",\r
+ mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],\r
+ BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,\r
+ BridgeResource->Length, BridgeResource->Alignment\r
+ ));\r
+ for ( Link = BridgeResource->ChildList.ForwardLink\r
+ ; Link != &BridgeResource->ChildList\r
+ ; Link = Link->ForwardLink\r
+ ) {\r
+ Resource = RESOURCE_NODE_FROM_LINK (Link);\r
+ if (Resource->ResourceUsage == PciResUsageTypical) {\r
+ Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;\r
+ DEBUG ((\r
+ EFI_D_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s ",\r
+ Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,\r
+ IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :\r
+ IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :\r
+ L"PCI"\r
+ ));\r
+\r
+ if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||\r
+ (IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||\r
+ (IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))\r
+ ) {\r
+ //\r
+ // The resource requirement comes from the device itself.\r
+ //\r
+ DEBUG ((\r
+ EFI_D_INFO, " [%02x|%02x|%02x:%02x]\n",\r
+ Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,\r
+ Resource->PciDev->FunctionNumber, Bar[Resource->Bar].Offset\r
+ ));\r
+ } else {\r
+ //\r
+ // The resource requirement comes from the subordinate devices.\r
+ //\r
+ DEBUG ((\r
+ EFI_D_INFO, " [%02x|%02x|%02x:**]\n",\r
+ Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,\r
+ Resource->PciDev->FunctionNumber\r
+ ));\r
+ }\r
+ } else {\r
+ DEBUG ((EFI_D_INFO, " Padding:Length = 0x%lx;\tAlignment = 0x%lx\n", Resource->Length, Resource->Alignment));\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Find the corresponding resource node for the Device in child list of BridgeResource.\r
+ \r
+ @param[in] Device Pointer to PCI_IO_DEVICE.\r
+ @param[in] BridgeResource Pointer to PCI_RESOURCE_NODE.\r
+ \r
+ @return !NULL The corresponding resource node for the Device.\r
+ @return NULL No corresponding resource node for the Device.\r
+**/\r
+PCI_RESOURCE_NODE *\r
+FindResourceNode (\r
+ IN PCI_IO_DEVICE *Device,\r
+ IN PCI_RESOURCE_NODE *BridgeResource\r
+ )\r
+{\r
+ LIST_ENTRY *Link;\r
+ PCI_RESOURCE_NODE *Resource;\r
+\r
+ for ( Link = BridgeResource->ChildList.ForwardLink\r
+ ; Link != &BridgeResource->ChildList\r
+ ; Link = Link->ForwardLink\r
+ ) {\r
+ Resource = RESOURCE_NODE_FROM_LINK (Link);\r
+ if (Resource->PciDev == Device) {\r
+ return Resource;\r
+ }\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Dump the resource map of all the devices under Bridge.\r
+ \r
+ @param[in] Bridge Bridge device instance.\r
+ @param[in] IoNode IO resource descriptor for the bridge device.\r
+ @param[in] Mem32Node Mem32 resource descriptor for the bridge device.\r
+ @param[in] PMem32Node PMem32 resource descriptor for the bridge device.\r
+ @param[in] Mem64Node Mem64 resource descriptor for the bridge device.\r
+ @param[in] PMem64Node PMem64 resource descriptor for the bridge device.\r
+**/\r
+VOID\r
+DumpResourceMap (\r
+ IN PCI_IO_DEVICE *Bridge,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ LIST_ENTRY *Link;\r
+ PCI_IO_DEVICE *Device;\r
+ PCI_RESOURCE_NODE *ChildIoNode;\r
+ PCI_RESOURCE_NODE *ChildMem32Node;\r
+ PCI_RESOURCE_NODE *ChildPMem32Node;\r
+ PCI_RESOURCE_NODE *ChildMem64Node;\r
+ PCI_RESOURCE_NODE *ChildPMem64Node;\r
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *ToText;\r
+ CHAR16 *Str;\r
+\r
+ DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Bridge->Handle,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ NULL,\r
+ NULL,\r
+ NULL,\r
+ EFI_OPEN_PROTOCOL_TEST_PROTOCOL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((\r
+ EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",\r
+ Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber\r
+ ));\r
+ } else {\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiDevicePathToTextProtocolGuid,\r
+ NULL,\r
+ (VOID **) &ToText\r
+ );\r
+ Str = NULL;\r
+ if (!EFI_ERROR (Status)) {\r
+ Str = ToText->ConvertDevicePathToText (\r
+ DevicePathFromHandle (Bridge->Handle),\r
+ FALSE,\r
+ FALSE\r
+ );\r
+ }\r
+ DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));\r
+ if (Str != NULL) {\r
+ FreePool (Str);\r
+ }\r
+ }\r
+\r
+ DumpBridgeResource (IoNode);\r
+ DumpBridgeResource (Mem32Node);\r
+ DumpBridgeResource (PMem32Node);\r
+ DumpBridgeResource (Mem64Node);\r
+ DumpBridgeResource (PMem64Node);\r
+ DEBUG ((EFI_D_INFO, "\n"));\r
+\r
+ for ( Link = Bridge->ChildList.ForwardLink\r
+ ; Link != &Bridge->ChildList\r
+ ; Link = Link->ForwardLink\r
+ ) {\r
+ Device = PCI_IO_DEVICE_FROM_LINK (Link);\r
+ if (IS_PCI_BRIDGE (&Device->Pci)) {\r
+\r
+ ChildIoNode = (IoNode == NULL ? NULL : FindResourceNode (Device, IoNode));\r
+ ChildMem32Node = (Mem32Node == NULL ? NULL : FindResourceNode (Device, Mem32Node));\r
+ ChildPMem32Node = (PMem32Node == NULL ? NULL : FindResourceNode (Device, PMem32Node));\r
+ ChildMem64Node = (Mem64Node == NULL ? NULL : FindResourceNode (Device, Mem64Node));\r
+ ChildPMem64Node = (PMem64Node == NULL ? NULL : FindResourceNode (Device, PMem64Node));\r
+\r
+ DumpResourceMap (\r
+ Device,\r
+ ChildIoNode,\r
+ ChildMem32Node,\r
+ ChildPMem32Node,\r
+ ChildMem64Node,\r
+ ChildPMem64Node\r
+ );\r
+ }\r
+ }\r
+}\r
+\r
/**\r
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
\r
RootBridgeDev,\r
0,\r
FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,\r
- 0,\r
+ RB_IO_RANGE,\r
PciBarTypeIo16,\r
PciResUsageTypical\r
);\r
RootBridgeDev,\r
0,\r
0xFFFFF,\r
- 0,\r
+ RB_MEM32_RANGE,\r
PciBarTypeMem32,\r
PciResUsageTypical\r
);\r
RootBridgeDev,\r
0,\r
0xFFFFF,\r
- 0,\r
+ RB_PMEM32_RANGE,\r
PciBarTypePMem32,\r
PciResUsageTypical\r
);\r
RootBridgeDev,\r
0,\r
0xFFFFF,\r
- 0,\r
+ RB_MEM64_RANGE,\r
PciBarTypeMem64,\r
PciResUsageTypical\r
);\r
RootBridgeDev,\r
0,\r
0xFFFFF,\r
- 0,\r
+ RB_PMEM64_RANGE,\r
PciBarTypePMem64,\r
PciResUsageTypical\r
);\r
RootBridgeDev->Handle,\r
AcpiConfig\r
);\r
+ //\r
+ // If SubmitResources returns error, PciBus isn't able to start.\r
+ // It's a fatal error so assertion is added.\r
+ //\r
+ DEBUG ((EFI_D_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
\r
//\r
// Notify platform to start to program the resource\r
//\r
Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
+ DEBUG ((EFI_D_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));\r
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
//\r
// If Hot Plug is not supported\r
//\r
REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,\r
+ EFI_IO_BUS_PCI | EFI_IOB_PCI_RES_ALLOC,\r
(VOID *) &HandleExtendedData,\r
sizeof (HandleExtendedData)\r
);\r
//\r
// Notify pci bus driver starts to program the resource\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
RootBridgeDev = NULL;\r
\r
// Create the entire system resource map from the information collected by\r
// enumerator. Several resource tree was created\r
//\r
- GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
+ IoBridge = FindResourceNode (RootBridgeDev, &IoPool);\r
+ Mem32Bridge = FindResourceNode (RootBridgeDev, &Mem32Pool);\r
+ PMem32Bridge = FindResourceNode (RootBridgeDev, &PMem32Pool);\r
+ Mem64Bridge = FindResourceNode (RootBridgeDev, &Mem64Pool);\r
+ PMem64Bridge = FindResourceNode (RootBridgeDev, &PMem64Pool);\r
+\r
+ ASSERT (IoBridge != NULL);\r
+ ASSERT (Mem32Bridge != NULL);\r
+ ASSERT (PMem32Bridge != NULL);\r
+ ASSERT (Mem64Bridge != NULL);\r
+ ASSERT (PMem64Bridge != NULL);\r
\r
//\r
// Program IO resources\r
PMem64Bridge\r
);\r
\r
+ IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;\r
+ Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;\r
+ PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;\r
+ Mem64Bridge ->PciDev->PciBar[Mem64Bridge ->Bar].BaseAddress = Mem64Base;\r
+ PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;\r
+\r
+ //\r
+ // Dump the resource map for current root bridge\r
+ //\r
+ DEBUG_CODE (\r
+ DumpResourceMap (\r
+ RootBridgeDev,\r
+ IoBridge,\r
+ Mem32Bridge,\r
+ PMem32Bridge,\r
+ Mem64Bridge,\r
+ PMem64Bridge\r
+ );\r
+ );\r
+\r
FreePool (AcpiConfig);\r
}\r
\r
//\r
// Notify the resource allocation phase is to end\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
\r
- return EFI_SUCCESS;\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Allocate NumberOfBuses buses and return the next available PCI bus number.\r
+\r
+ @param Bridge Bridge device instance.\r
+ @param StartBusNumber Current available PCI bus number.\r
+ @param NumberOfBuses Number of buses enumerated below the StartBusNumber.\r
+ @param NextBusNumber Next available PCI bus number.\r
+\r
+ @retval EFI_SUCCESS Available bus number resource is enough. Next available PCI bus number\r
+ is returned in NextBusNumber.\r
+ @retval EFI_OUT_OF_RESOURCES Available bus number resource is not enough for allocation.\r
+\r
+**/\r
+EFI_STATUS\r
+PciAllocateBusNumber (\r
+ IN PCI_IO_DEVICE *Bridge,\r
+ IN UINT8 StartBusNumber,\r
+ IN UINT8 NumberOfBuses,\r
+ OUT UINT8 *NextBusNumber\r
+ )\r
+{\r
+ PCI_IO_DEVICE *RootBridge;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;\r
+ UINT8 NextNumber;\r
+ UINT64 MaxNumberInRange;\r
+\r
+ //\r
+ // Get PCI Root Bridge device\r
+ //\r
+ RootBridge = Bridge;\r
+ while (RootBridge->Parent != NULL) {\r
+ RootBridge = RootBridge->Parent;\r
+ }\r
+\r
+ //\r
+ // Get next available PCI bus number\r
+ //\r
+ BusNumberRanges = RootBridge->BusNumberRanges;\r
+ while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
+ MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;\r
+ if (StartBusNumber >= BusNumberRanges->AddrRangeMin && StartBusNumber <= MaxNumberInRange) {\r
+ NextNumber = (UINT8)(StartBusNumber + NumberOfBuses);\r
+ while (NextNumber > MaxNumberInRange) {\r
+ ++BusNumberRanges;\r
+ if (BusNumberRanges->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ NextNumber = (UINT8)(NextNumber + (BusNumberRanges->AddrRangeMin - (MaxNumberInRange + 1)));\r
+ MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;\r
+ }\r
+ *NextBusNumber = NextNumber;\r
+ return EFI_SUCCESS;\r
+ }\r
+ BusNumberRanges++;\r
+ }\r
+ return EFI_OUT_OF_RESOURCES;\r
}\r
\r
/**\r
continue;\r
}\r
\r
- DEBUG((EFI_D_INFO, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
-\r
//\r
// Get the PCI device information\r
//\r
}\r
}\r
\r
- //\r
- // Add feature to support customized secondary bus number\r
- //\r
- if (*SubBusNumber == 0) {\r
- *SubBusNumber = *PaddedBusRange;\r
- *PaddedBusRange = 0;\r
+ Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
}\r
-\r
- (*SubBusNumber)++;\r
SecondBus = *SubBusNumber;\r
\r
Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
EfiPciBeforeChildBusEnumeration\r
);\r
\r
- DEBUG((EFI_D_INFO, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber));\r
Status = PciScanBus (\r
PciDevice,\r
(UINT8) (SecondBus),\r
(State & EFI_HPC_STATE_INITIALIZED) != 0) {\r
*PaddedBusRange = (UINT8) ((UINT8) (BusRange) +*PaddedBusRange);\r
} else {\r
- *SubBusNumber = (UINT8) ((UINT8) (BusRange) +*SubBusNumber);\r
+ Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8) (BusRange), SubBusNumber);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
}\r
}\r
\r
if (PcdGetBool (PcdSrIovSupport) && PciDevice->SrIovCapabilityOffset != 0) {\r
if (TempReservedBusNum < PciDevice->ReservedBusNum) {\r
\r
- (*SubBusNumber) = (UINT8)((*SubBusNumber) + PciDevice->ReservedBusNum - TempReservedBusNum);\r
+ Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8) (PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
TempReservedBusNum = PciDevice->ReservedBusNum;\r
\r
if (Func == 0) {\r
//\r
REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_HPC_INIT,\r
+ EFI_IO_BUS_PCI | EFI_IOB_PCI_HPC_INIT,\r
Temp->DevicePath\r
);\r
\r
//\r
// Notify the bus allocation phase is about to start\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
DEBUG((EFI_D_INFO, "PCI Bus First Scanning\n"));\r
RootBridgeHandle = NULL;\r
//\r
// Notify the bus allocation phase is about to start for the 2nd time\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
DEBUG((EFI_D_INFO, "PCI Bus Second Scanning\n"));\r
RootBridgeHandle = NULL;\r
//\r
// Notify the resource allocation phase is to start\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);\r
+ Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
RootBridgeHandle = NULL;\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
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