/** @file\r
PCI Rom supporting funtions implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
}\r
\r
//\r
- // The PCI Data Structure must be DWORD aligned. \r
+ // The PCI Data Structure must be DWORD aligned.\r
//\r
if (RomHeader->PcirOffset == 0 ||\r
(RomHeader->PcirOffset & 3) != 0 ||\r
FirstCheck = FALSE;\r
OffsetPcir = RomHeader->PcirOffset;\r
//\r
- // If the pointer to the PCI Data Structure is invalid, no further images can be located. \r
- // The PCI Data Structure must be DWORD aligned. \r
+ // If the pointer to the PCI Data Structure is invalid, no further images can be located.\r
+ // The PCI Data Structure must be DWORD aligned.\r
//\r
if (OffsetPcir == 0 ||\r
(OffsetPcir & 3) != 0 ||\r
PciDevice->BusNumber,\r
PciDevice->DeviceNumber,\r
PciDevice->FunctionNumber,\r
- (UINT64) (UINTN) PciDevice->PciIo.RomImage,\r
+ PciDevice->PciIo.RomImage,\r
PciDevice->PciIo.RomSize\r
);\r
\r
)\r
{\r
UINT32 Value32;\r
- UINT32 Offset;\r
- UINT32 OffsetMax;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
\r
PciIo = &PciDevice->PciIo;\r
if (Enable) {\r
- //\r
- // Clear all bars\r
- //\r
- OffsetMax = 0x24;\r
- if (IS_PCI_BRIDGE(&PciDevice->Pci)) {\r
- OffsetMax = 0x14;\r
- }\r
-\r
- for (Offset = 0x10; Offset <= OffsetMax; Offset += sizeof (UINT32)) {\r
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
- }\r
\r
//\r
// set the Rom base address: now is hardcode\r
//\r
// Programe all upstream bridge\r
//\r
- ProgrameUpstreamBridgeForRom(PciDevice, RomBar, TRUE);\r
+ ProgramUpstreamBridgeForRom (PciDevice, RomBar, TRUE);\r
\r
//\r
// Setting the memory space bit in the function's command register\r
//\r
// Destroy the programmed bar in all the upstream bridge.\r
//\r
- ProgrameUpstreamBridgeForRom(PciDevice, RomBar, FALSE);\r
+ ProgramUpstreamBridgeForRom (PciDevice, RomBar, FALSE);\r
\r
//\r
// disable rom decode\r
BufferSize,\r
&ImageHandle\r
);\r
-\r
- FreePool (PciOptionRomImageDevicePath);\r
-\r
- if (!EFI_ERROR (Status)) {\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Record the Option ROM Image device path when LoadImage fails.\r
+ // PciOverride.GetDriver() will try to look for the Image Handle using the device path later.\r
+ //\r
+ AddDriver (PciDevice, NULL, PciOptionRomImageDevicePath);\r
+ } else {\r
Status = gBS->StartImage (ImageHandle, NULL, NULL);\r
if (!EFI_ERROR (Status)) {\r
- AddDriver (PciDevice, ImageHandle);\r
+ //\r
+ // Record the Option ROM Image Handle\r
+ //\r
+ AddDriver (PciDevice, ImageHandle, NULL);\r
PciRomAddImageMapping (\r
ImageHandle,\r
PciDevice->PciRootBridgeIo->SegmentNumber,\r
PciDevice->BusNumber,\r
PciDevice->DeviceNumber,\r
PciDevice->FunctionNumber,\r
- (UINT64) (UINTN) PciDevice->PciIo.RomImage,\r
+ PciDevice->PciIo.RomImage,\r
PciDevice->PciIo.RomSize\r
);\r
RetStatus = EFI_SUCCESS;\r
}\r
}\r
+ FreePool (PciOptionRomImageDevicePath);\r
\r
NextImage:\r
RomBarOffset += ImageSize;\r