MdeModulePkg/PciHostBridgeDxe: Honor ResourceAssigned

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciHostBridgeDxe / PciRootBridgeIo.c

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index dbb415ac2d6e12764c33ffa6af4e78bf68ca8c78..78811419bf8df580e21864208d54941df10f4fb9 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -59,20 +59,19 @@ UINT8 mOutStride[] = {
   Construct the Pci Root Bridge instance.\r
 \r
   @param Bridge            The root bridge instance.\r
-  @param HostBridgeHandle  Handle to the HostBridge.\r
 \r
   @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created\r
           or NULL if creation fails.\r
 **/\r
 PCI_ROOT_BRIDGE_INSTANCE *\r
 CreateRootBridge (\r
-  IN PCI_ROOT_BRIDGE       *Bridge,\r
-  IN EFI_HANDLE            HostBridgeHandle\r
+  IN PCI_ROOT_BRIDGE       *Bridge\r
   )\r
 {\r
   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
   PCI_RESOURCE_TYPE        Index;\r
   CHAR16                   *DevicePathStr;\r
+  PCI_ROOT_BRIDGE_APERTURE *Aperture;\r
 \r
   DevicePathStr = NULL;\r
 \r
@@ -120,32 +119,37 @@ CreateRootBridge (
     }\r
   }\r
 \r
-  if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
-    //\r
-    // If this bit is set, then the PCI Root Bridge does not\r
-    // support separate windows for Non-prefetchable and Prefetchable\r
-    // memory.\r
-    //\r
-    ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
-    ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
-    if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
-        (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
-        ) {\r
-      return NULL;\r
+  //\r
+  // Ignore AllocationAttributes when resources were already assigned.\r
+  //\r
+  if (!Bridge->ResourceAssigned) {\r
+    if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
+      //\r
+      // If this bit is set, then the PCI Root Bridge does not\r
+      // support separate windows for Non-prefetchable and Prefetchable\r
+      // memory.\r
+      //\r
+      ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
+      ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+      if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
+          (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
+          ) {\r
+        return NULL;\r
+      }\r
     }\r
-  }\r
 \r
-  if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r
-    //\r
-    // If this bit is not set, then the PCI Root Bridge does not support\r
-    // 64 bit memory windows.\r
-    //\r
-    ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
-    ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
-    if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
-        (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
-        ) {\r
-      return NULL;\r
+    if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r
+      //\r
+      // If this bit is not set, then the PCI Root Bridge does not support\r
+      // 64 bit memory windows.\r
+      //\r
+      ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
+      ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+      if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
+          (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
+          ) {\r
+        return NULL;\r
+      }\r
     }\r
   }\r
 \r
@@ -174,14 +178,42 @@ CreateRootBridge (
   CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
 \r
   for (Index = TypeIo; Index < TypeMax; Index++) {\r
-    RootBridge->ResAllocNode[Index].Type   = Index;\r
-    RootBridge->ResAllocNode[Index].Base   = 0;\r
-    RootBridge->ResAllocNode[Index].Length = 0;\r
-    RootBridge->ResAllocNode[Index].Status = ResNone;\r
+    switch (Index) {\r
+    case TypeBus:\r
+      Aperture = &RootBridge->Bus;\r
+      break;\r
+    case TypeIo:\r
+      Aperture = &RootBridge->Io;\r
+      break;\r
+    case TypeMem32:\r
+      Aperture = &RootBridge->Mem;\r
+      break;\r
+    case TypeMem64:\r
+      Aperture = &RootBridge->MemAbove4G;\r
+      break;\r
+    case TypePMem32:\r
+      Aperture = &RootBridge->PMem;\r
+      break;\r
+    case TypePMem64:\r
+      Aperture = &RootBridge->PMemAbove4G;\r
+      break;\r
+    default:\r
+      ASSERT (FALSE);\r
+      break;\r
+    }\r
+    RootBridge->ResAllocNode[Index].Type     = Index;\r
+    if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {\r
+      RootBridge->ResAllocNode[Index].Base   = Aperture->Base;\r
+      RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;\r
+      RootBridge->ResAllocNode[Index].Status = ResAllocated;\r
+    } else {\r
+      RootBridge->ResAllocNode[Index].Base   = 0;\r
+      RootBridge->ResAllocNode[Index].Length = 0;\r
+      RootBridge->ResAllocNode[Index].Status = ResNone;\r
+    }\r
   }\r
 \r
   RootBridge->RootBridgeIo.SegmentNumber  = Bridge->Segment;\r
-  RootBridge->RootBridgeIo.ParentHandle   = HostBridgeHandle;\r
   RootBridge->RootBridgeIo.PollMem        = RootBridgeIoPollMem;\r
   RootBridge->RootBridgeIo.PollIo         = RootBridgeIoPollIo;\r
   RootBridge->RootBridgeIo.Mem.Read       = RootBridgeIoMemRead;\r