MdeModulePkg/PciHostBridgeDxe: Fix a Base/Limit comparing bug

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciHostBridgeDxe / PciRootBridgeIo.c

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 9f756e4c56f73532bd589b34d10260567c73456e..dbb415ac2d6e12764c33ffa6af4e78bf68ca8c78 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -95,25 +95,25 @@ CreateRootBridge (
   //\r
   // Make sure Mem and MemAbove4G apertures are valid\r
   //\r
-  if (Bridge->Mem.Base < Bridge->Mem.Limit) {\r
+  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {\r
     ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r
     if (Bridge->Mem.Limit >= SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) {\r
+  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {\r
     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r
     if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->PMem.Base < Bridge->PMem.Limit) {\r
+  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {\r
     ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r
     if (Bridge->PMem.Limit >= SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) {\r
+  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {\r
     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r
     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r
       return NULL;\r
@@ -126,10 +126,10 @@ CreateRootBridge (
     // support separate windows for Non-prefetchable and Prefetchable\r
     // memory.\r
     //\r
-    ASSERT (Bridge->PMem.Base >= Bridge->PMem.Limit);\r
-    ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);\r
-    if ((Bridge->PMem.Base < Bridge->PMem.Limit) ||\r
-        (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)\r
+    ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
+    ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+    if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
+        (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
         ) {\r
       return NULL;\r
     }\r
@@ -140,10 +140,10 @@ CreateRootBridge (
     // If this bit is not set, then the PCI Root Bridge does not support\r
     // 64 bit memory windows.\r
     //\r
-    ASSERT (Bridge->MemAbove4G.Base >= Bridge->MemAbove4G.Limit);\r
-    ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);\r
-    if ((Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) ||\r
-        (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)\r
+    ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
+    ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+    if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
+        (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
         ) {\r
       return NULL;\r
     }\r