/*++\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Module Name:\r
\r
\r
//-------------------------------------------------------------------------\r
// Offsets to the various registers.\r
-// All accesses need not be longword aligned. \r
+// All accesses need not be longword aligned.\r
//-------------------------------------------------------------------------\r
enum speedo_offsets {\r
- SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status. \r
- SCBPointer = 4, // General purpose pointer. \r
- SCBPort = 8, // Misc. commands and operands. \r
- SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control. \r
- SCBCtrlMDI = 16, // MDI interface control. \r
- SCBEarlyRx = 20, // Early receive byte count. \r
+ SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r
+ SCBPointer = 4, // General purpose pointer.\r
+ SCBPort = 8, // Misc. commands and operands.\r
+ SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r
+ SCBCtrlMDI = 16, // MDI interface control.\r
+ SCBEarlyRx = 20, // Early receive byte count.\r
SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r
// offsets for general control registers (GCRs)\r
SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r
#define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r
\r
//-------------------------------------------------------------------------\r
-// Action commands - Commands that can be put in a command list entry. \r
+// Action commands - Commands that can be put in a command list entry.\r
//-------------------------------------------------------------------------\r
enum commands {\r
CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r
#define BIT_4_6 0x0070\r
#define BIT_4_7 0x00F0\r
#define BIT_5_7 0x00E0\r
-#define BIT_5_9 0x03E0 \r
+#define BIT_5_9 0x03E0\r
#define BIT_5_12 0x1FE0\r
#define BIT_5_15 0xFFE0\r
#define BIT_6_7 0x00c0\r
UINT64 Unique_ID;\r
\r
EFI_PCI_IO_PROTOCOL *Io_Function;\r
+ //\r
+ // Original PCI attributes\r
+ //\r
+ UINT64 OriginalPciAttributes;\r
\r
VOID (*Delay_30)(UINTN); // call back routine\r
VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r