MdeModulePkg/XhciDxe: Check timeout URB again after stopping endpoint

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
index 023c1089f29c78d93a737885702377fb6ad4aac7..f40f94c1e4b711acf47b37adb4f4964cb0c129ac 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
@@ -2,7 +2,7 @@
 \r
   This file contains the definition for XHCI host controller schedule routines.\r
 \r
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -80,6 +80,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define TRB_COMPLETION_TRB_ERROR              5\r
 #define TRB_COMPLETION_STALL_ERROR            6\r
 #define TRB_COMPLETION_SHORT_PACKET           13\r
+#define TRB_COMPLETION_STOPPED                26\r
+#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
 \r
 //\r
 // The topology string used to present usb device location\r
@@ -224,7 +226,7 @@ typedef struct _TRANSFER_TRB_NORMAL {
 \r
   UINT32                  TRBPtrHi;\r
 \r
-  UINT32                  Lenth:17;\r
+  UINT32                  Length:17;\r
   UINT32                  TDSize:5;\r
   UINT32                  IntTarget:10;\r
 \r
@@ -253,7 +255,7 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP {
   UINT32                  wIndex:16;\r
   UINT32                  wLength:16;\r
 \r
-  UINT32                  Lenth:17;\r
+  UINT32                  Length:17;\r
   UINT32                  RsvdZ1:5;\r
   UINT32                  IntTarget:10;\r
 \r
@@ -276,7 +278,7 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA {
 \r
   UINT32                  TRBPtrHi;\r
 \r
-  UINT32                  Lenth:17;\r
+  UINT32                  Length:17;\r
   UINT32                  TDSize:5;\r
   UINT32                  IntTarget:10;\r
 \r
@@ -325,7 +327,7 @@ typedef struct _EVT_TRB_TRANSFER {
 \r
   UINT32                  TRBPtrHi;\r
 \r
-  UINT32                  Lenth:24;\r
+  UINT32                  Length:24;\r
   UINT32                  Completecode:8;\r
 \r
   UINT32                  CycleBit:1;\r
@@ -1317,6 +1319,88 @@ XhcRecoverHaltedEndpoint (
   IN  URB                 *Urb\r
   );\r
 \r
+/**\r
+  System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
+  Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
+  the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
+  state.\r
+\r
+  @param  Xhc                   The XHCI Instance.\r
+  @param  Urb                   The urb which doesn't get completed in a specified timeout range.\r
+\r
+  @retval EFI_SUCCESS           The dequeuing of the TDs is successful.\r
+  @retval Others                Failed to stop the endpoint and dequeue the TDs.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcDequeueTrbFromEndpoint (\r
+  IN  USB_XHCI_INSTANCE   *Xhc,\r
+  IN  URB                 *Urb\r
+  );\r
+\r
+/**\r
+  Stop endpoint through XHCI's Stop_Endpoint cmd.\r
+\r
+  @param  Xhc                   The XHCI Instance.\r
+  @param  SlotId                The slot id to be configured.\r
+  @param  Dci                   The device context index of endpoint.\r
+  @param  PendingUrb            The pending URB to check completion status when stopping the end point.\r
+\r
+  @retval EFI_SUCCESS           Stop endpoint successfully.\r
+  @retval Others                Failed to stop endpoint.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcStopEndpoint (\r
+  IN USB_XHCI_INSTANCE      *Xhc,\r
+  IN UINT8                  SlotId,\r
+  IN UINT8                  Dci,\r
+  IN URB                    *PendingUrb  OPTIONAL\r
+  );\r
+\r
+/**\r
+  Reset endpoint through XHCI's Reset_Endpoint cmd.\r
+\r
+  @param  Xhc                   The XHCI Instance.\r
+  @param  SlotId                The slot id to be configured.\r
+  @param  Dci                   The device context index of endpoint.\r
+\r
+  @retval EFI_SUCCESS           Reset endpoint successfully.\r
+  @retval Others                Failed to reset endpoint.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcResetEndpoint (\r
+  IN USB_XHCI_INSTANCE      *Xhc,\r
+  IN UINT8                  SlotId,\r
+  IN UINT8                  Dci\r
+  );\r
+\r
+/**\r
+  Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
+\r
+  @param  Xhc                   The XHCI Instance.\r
+  @param  SlotId                The slot id to be configured.\r
+  @param  Dci                   The device context index of endpoint.\r
+  @param  Urb                   The dequeue pointer of the transfer ring specified\r
+                                by the urb to be updated.\r
+\r
+  @retval EFI_SUCCESS           Set transfer ring dequeue pointer succeeds.\r
+  @retval Others                Failed to set transfer ring dequeue pointer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+XhcSetTrDequeuePointer (\r
+  IN USB_XHCI_INSTANCE      *Xhc,\r
+  IN UINT8                  SlotId,\r
+  IN UINT8                  Dci,\r
+  IN URB                    *Urb\r
+  );\r
+\r
 /**\r
   Create a new URB for a new transaction.\r
 \r