MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Bus / Ufs / UfsBlockIoPei / UfsHci.c

diff --git a/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c b/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c
index 55c780627966d53c0b7f2cecb2eb0bacf1c410a8..e36ff8c02aabb495817530fabf9f61aaa7350cf8 100644 (file)
--- a/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -108,13 +108,13 @@ DumpUicCmdExecResult (
         break;\r
       case 0x08:\r
         DEBUG ((EFI_D_VERBOSE, "UIC configuration command fails - PEER_COMMUNICATION_FAILURE\n"));\r
-        break; \r
+        break;\r
       case 0x09:\r
         DEBUG ((EFI_D_VERBOSE, "UIC configuration command fails - BUSY\n"));\r
         break;\r
       case 0x0A:\r
         DEBUG ((EFI_D_VERBOSE, "UIC configuration command fails - DME_FAILURE\n"));\r
-        break;        \r
+        break;\r
       default :\r
         ASSERT (FALSE);\r
         break;\r
@@ -125,7 +125,7 @@ DumpUicCmdExecResult (
         break;\r
       case 0x01:\r
         DEBUG ((EFI_D_VERBOSE, "UIC control command fails - FAILURE\n"));\r
-        break;     \r
+        break;\r
       default :\r
         ASSERT (FALSE);\r
         break;\r
@@ -171,7 +171,7 @@ DumpQueryResponseResult (
       break;\r
     case 0xFE:\r
       DEBUG ((EFI_D_VERBOSE, "Query Response with Invalid Opcode\n"));\r
-      break; \r
+      break;\r
     case 0xFF:\r
       DEBUG ((EFI_D_VERBOSE, "Query Response with General Failure\n"));\r
       break;\r
@@ -243,7 +243,7 @@ UfsFillTsfOfQueryReqUpiu (
       SwapLittleEndianToBigEndian ((UINT8*)&Length, sizeof (Length));\r
       TsfBase->Length = Length;\r
     }\r
-  \r
+\r
     if (Opcode == UtpQueryFuncOpcodeWrAttr) {\r
       SwapLittleEndianToBigEndian ((UINT8*)&Value, sizeof (Value));\r
       TsfBase->Value  = Value;\r
@@ -731,7 +731,7 @@ VOID
 UfsStartExecCmd (\r
   IN  UFS_PEIM_HC_PRIVATE_DATA     *Private,\r
   IN  UINT8                        Slot\r
-  ) \r
+  )\r
 {\r
   UINTN         UfsHcBase;\r
   UINTN         Address;\r
@@ -739,7 +739,7 @@ UfsStartExecCmd (
 \r
   UfsHcBase = Private->UfsHcBase;\r
 \r
-  Address = UfsHcBase + UFS_HC_UTRLRSR_OFFSET;  \r
+  Address = UfsHcBase + UFS_HC_UTRLRSR_OFFSET;\r
   Data    = MmioRead32 (Address);\r
   if ((Data & UFS_HC_UTRLRSR) != UFS_HC_UTRLRSR) {\r
     MmioWrite32 (Address, UFS_HC_UTRLRSR);\r
@@ -760,7 +760,7 @@ VOID
 UfsStopExecCmd (\r
   IN  UFS_PEIM_HC_PRIVATE_DATA     *Private,\r
   IN  UINT8                        Slot\r
-  ) \r
+  )\r
 {\r
   UINTN         UfsHcBase;\r
   UINTN         Address;\r
@@ -768,10 +768,10 @@ UfsStopExecCmd (
 \r
   UfsHcBase = Private->UfsHcBase;\r
 \r
-  Address = UfsHcBase + UFS_HC_UTRLDBR_OFFSET;  \r
+  Address = UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
   Data    = MmioRead32 (Address);\r
   if ((Data & (BIT0 << Slot)) != 0) {\r
-    Address = UfsHcBase + UFS_HC_UTRLCLR_OFFSET;  \r
+    Address = UfsHcBase + UFS_HC_UTRLCLR_OFFSET;\r
     Data    = MmioRead32 (Address);\r
     MmioWrite32 (Address, (Data & ~(BIT0 << Slot)));\r
   }\r
@@ -839,7 +839,7 @@ UfsRwDeviceDesc (
   if (EFI_ERROR (Status)) {\r
     return Status;\r
   }\r
-  \r
+\r
   Trd = ((UTP_TRD*)Private->UtpTrlBase) + Slot;\r
   //\r
   // Fill transfer request descriptor to this slot.\r
@@ -863,8 +863,8 @@ UfsRwDeviceDesc (
 \r
   //\r
   // Wait for the completion of the transfer request.\r
-  //  \r
-  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;  \r
+  //\r
+  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
   Status = UfsWaitMemSet (Address, BIT0 << Slot, 0, Packet.Timeout);\r
   if (EFI_ERROR (Status)) {\r
     goto Exit;\r
@@ -953,7 +953,7 @@ UfsRwAttributes (
   if (EFI_ERROR (Status)) {\r
     return Status;\r
   }\r
-  \r
+\r
   Trd = ((UTP_TRD*)Private->UtpTrlBase) + Slot;\r
   //\r
   // Fill transfer request descriptor to this slot.\r
@@ -977,8 +977,8 @@ UfsRwAttributes (
 \r
   //\r
   // Wait for the completion of the transfer request.\r
-  //  \r
-  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;  \r
+  //\r
+  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
   Status = UfsWaitMemSet (Address, BIT0 << Slot, 0, Packet.Timeout);\r
   if (EFI_ERROR (Status)) {\r
     goto Exit;\r
@@ -1091,8 +1091,8 @@ UfsRwFlags (
 \r
   //\r
   // Wait for the completion of the transfer request.\r
-  //  \r
-  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;  \r
+  //\r
+  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
   Status = UfsWaitMemSet (Address, BIT0 << Slot, 0, Packet.Timeout);\r
   if (EFI_ERROR (Status)) {\r
     goto Exit;\r
@@ -1249,8 +1249,8 @@ UfsExecNopCmds (
 \r
   //\r
   // Wait for the completion of the transfer request.\r
-  //  \r
-  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;  \r
+  //\r
+  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
   Status = UfsWaitMemSet (Address, BIT0 << Slot, 0, UFS_TIMEOUT);\r
   if (EFI_ERROR (Status)) {\r
     goto Exit;\r
@@ -1335,8 +1335,8 @@ UfsExecScsiCmds (
 \r
   //\r
   // Wait for the completion of the transfer request.\r
-  //  \r
-  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;  \r
+  //\r
+  Address = Private->UfsHcBase + UFS_HC_UTRLDBR_OFFSET;\r
   Status = UfsWaitMemSet (Address, BIT0 << Slot, 0, Packet->Timeout);\r
   if (EFI_ERROR (Status)) {\r
     goto Exit;\r
@@ -1348,7 +1348,7 @@ UfsExecScsiCmds (
   Response     = (UTP_RESPONSE_UPIU*)(CmdDescBase + Trd->RuO * sizeof (UINT32));\r
   SenseDataLen = Response->SenseDataLen;\r
   SwapLittleEndianToBigEndian ((UINT8*)&SenseDataLen, sizeof (UINT16));\r
-  \r
+\r
   if ((Packet->SenseDataLength != 0) && (Packet->SenseData != NULL)) {\r
     CopyMem (Packet->SenseData, Response->SenseData, SenseDataLen);\r
     Packet->SenseDataLength = (UINT8)SenseDataLen;\r
@@ -1458,7 +1458,7 @@ UfsExecUicCommands (
 \r
   //\r
   // UFS 2.0 spec section 5.3.1 Offset:0x20 IS.Bit10 UIC Command Completion Status (UCCS)\r
-  // This bit is set to '1' by the host controller upon completion of a UIC command. \r
+  // This bit is set to '1' by the host controller upon completion of a UIC command.\r
   //\r
   Address = UfsHcBase + UFS_HC_IS_OFFSET;\r
   Data    = MmioRead32 (Address);\r
@@ -1481,7 +1481,7 @@ UfsExecUicCommands (
   //\r
   // Check value of HCS.DP and make sure that there is a device attached to the Link.\r
   //\r
-  Address = UfsHcBase + UFS_HC_STATUS_OFFSET;  \r
+  Address = UfsHcBase + UFS_HC_STATUS_OFFSET;\r
   Data    = MmioRead32 (Address);\r
   if ((Data & UFS_HC_HCS_DP) == 0) {\r
     Address = UfsHcBase + UFS_HC_IS_OFFSET;\r
@@ -1614,11 +1614,11 @@ UfsInitTaskManagementRequestList (
   EFI_PHYSICAL_ADDRESS   CmdDescPhyAddr;\r
   VOID                   *CmdDescMapping;\r
   EFI_STATUS             Status;\r
-  \r
+\r
   //\r
   // Initial h/w and s/w context for future operations.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET;\r
   Data    = MmioRead32 (Address);\r
   Private->Capabilities = Data;\r
 \r
@@ -1642,9 +1642,9 @@ UfsInitTaskManagementRequestList (
   // Program the UTP Task Management Request List Base Address and UTP Task Management\r
   // Request List Base Address with a 64-bit address allocated at step 6.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_UTMRLBA_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTMRLBA_OFFSET;\r
   MmioWrite32 (Address, (UINT32)(UINTN)CmdDescPhyAddr);\r
-  Address = Private->UfsHcBase + UFS_HC_UTMRLBAU_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTMRLBAU_OFFSET;\r
   MmioWrite32 (Address, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));\r
   Private->UtpTmrlBase = (VOID*)(UINTN)CmdDescHost;\r
   Private->Nutmrs      = Nutmrs;\r
@@ -1654,7 +1654,7 @@ UfsInitTaskManagementRequestList (
   // Enable the UTP Task Management Request List by setting the UTP Task Management\r
   // Request List RunStop Register (UTMRLRSR) to '1'.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET;\r
   MmioWrite32 (Address, UFS_HC_UTMRLRSR);\r
 \r
   return EFI_SUCCESS;\r
@@ -1681,11 +1681,11 @@ UfsInitTransferRequestList (
   EFI_PHYSICAL_ADDRESS   CmdDescPhyAddr;\r
   VOID                   *CmdDescMapping;\r
   EFI_STATUS             Status;\r
-  \r
+\r
   //\r
   // Initial h/w and s/w context for future operations.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_CAP_OFFSET;\r
   Data    = MmioRead32 (Address);\r
   Private->Capabilities = Data;\r
 \r
@@ -1709,19 +1709,19 @@ UfsInitTransferRequestList (
   // Program the UTP Transfer Request List Base Address and UTP Transfer Request List\r
   // Base Address with a 64-bit address allocated at step 8.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_UTRLBA_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTRLBA_OFFSET;\r
   MmioWrite32 (Address, (UINT32)(UINTN)CmdDescPhyAddr);\r
-  Address = Private->UfsHcBase + UFS_HC_UTRLBAU_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTRLBAU_OFFSET;\r
   MmioWrite32 (Address, (UINT32)RShiftU64 ((UINT64)CmdDescPhyAddr, 32));\r
   Private->UtpTrlBase = (VOID*)(UINTN)CmdDescHost;\r
   Private->Nutrs      = Nutrs;\r
   Private->TrlMapping = CmdDescMapping;\r
-  \r
+\r
   //\r
   // Enable the UTP Transfer Request List by setting the UTP Transfer Request List\r
   // RunStop Register (UTRLRSR) to '1'.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET;\r
   MmioWrite32 (Address, UFS_HC_UTRLRSR);\r
 \r
   return EFI_SUCCESS;\r
@@ -1803,14 +1803,14 @@ UfsControllerStop (
   // Enable the UTP Task Management Request List by setting the UTP Task Management\r
   // Request List RunStop Register (UTMRLRSR) to '1'.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTMRLRSR_OFFSET;\r
   MmioWrite32 (Address, 0);\r
 \r
   //\r
   // Enable the UTP Transfer Request List by setting the UTP Transfer Request List\r
   // RunStop Register (UTRLRSR) to '1'.\r
   //\r
-  Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET;  \r
+  Address = Private->UfsHcBase + UFS_HC_UTRLRSR_OFFSET;\r
   MmioWrite32 (Address, 0);\r
 \r
   //\r