MdeModulePkg: Clean up source files

[mirror_edk2.git] / MdeModulePkg / Include / Ppi / AtaController.h

diff --git a/MdeModulePkg/Include/Ppi/AtaController.h b/MdeModulePkg/Include/Ppi/AtaController.h
index 2333bef6aa657f3eda4e53a3339fb27acc031ea5..a24b496f9c0e8559149c898a0a0cd223682bc47b 100644 (file)
--- a/MdeModulePkg/Include/Ppi/AtaController.h
+++ b/MdeModulePkg/Include/Ppi/AtaController.h
@@ -1,8 +1,8 @@
 /** @file\r
   Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve\r
   the base I/O port address for each of the enabled IDE and SATA channels.\r
-  \r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
@@ -19,7 +19,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define _PEI_ATA_CONTROLLER_PPI_H_\r
 \r
 ///\r
-/// Global ID for the PEI_ATA_CONTROLLER_PPI. \r
+/// Global ID for the PEI_ATA_CONTROLLER_PPI.\r
 ///\r
 #define PEI_ATA_CONTROLLER_PPI_GUID \\r
   { \\r
@@ -32,50 +32,50 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI;\r
 \r
 ///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
-/// disable the IDE channels. \r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
+/// disable the IDE channels.\r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
 #define PEI_ICH_IDE_NONE        0x00\r
 \r
 ///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
 /// enable the Primary IDE channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
 #define PEI_ICH_IDE_PRIMARY     0x01\r
 \r
 ///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
 /// enable the Secondary IDE channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
 #define PEI_ICH_IDE_SECONDARY   0x02\r
 \r
 ///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
 /// disable the SATA channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
 #define PEI_ICH_SATA_NONE       0x04\r
 \r
 ///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
 /// enable the Primary SATA channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
 #define PEI_ICH_SATA_PRIMARY    0x08\r
 \r
 ///\r
-/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to \r
+/// This bit is used in the ChannelMask parameter of EnableAtaChannel() to\r
 /// enable the Secondary SATA channel.\r
-/// This is designed for old generation chipset with PATA/SATA controllers. \r
-/// It may be ignored in PPI implementation for new generation chipset without PATA controller. \r
+/// This is designed for old generation chipset with PATA/SATA controllers.\r
+/// It may be ignored in PPI implementation for new generation chipset without PATA controller.\r
 ///\r
 #define PEI_ICH_SATA_SECONDARY  0x010\r
 \r
@@ -97,15 +97,15 @@ typedef struct {
   Sets IDE and SATA channels to an enabled or disabled state.\r
 \r
   This service enables or disables the IDE and SATA channels specified by ChannelMask.\r
-  It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy. \r
-  The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function. \r
+  It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy.\r
+  The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.\r
 \r
   If the new state is set, then EFI_SUCCESS is returned.  If the new state can\r
   not be set, then EFI_DEVICE_ERROR is returned.\r
 \r
   @param[in] PeiServices   The pointer to the PEI Services Table.\r
   @param[in] This          The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r
-  @param[in] ChannelMask   The bitmask that identifies the IDE and SATA channels to \r
+  @param[in] ChannelMask   The bitmask that identifies the IDE and SATA channels to\r
                            enable or disable. This parameter is optional.\r
 \r
   @retval EFI_SUCCESS        The IDE or SATA channels were enabled or disabled successfully.\r
@@ -121,18 +121,18 @@ EFI_STATUS
   );\r
 \r
 /**\r
-  Retrieves the I/O port base addresses for command and control registers of the \r
+  Retrieves the I/O port base addresses for command and control registers of the\r
   enabled IDE/SATA channels.\r
 \r
   This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O\r
   port base addresses for the command and control registers of the IDE and SATA\r
-  channels that were previously enabled in EnableAtaChannel().  The number of \r
+  channels that were previously enabled in EnableAtaChannel().  The number of\r
   enabled IDE and SATA channels is returned.\r
 \r
   @param[in]  PeiServices       The pointer to the PEI Services Table.\r
   @param[in]  This              The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.\r
-  @param[out] IdeRegsBaseAddr   The pointer to caller allocated space to return the \r
-                                I/O port base addresses of the IDE and SATA channels \r
+  @param[out] IdeRegsBaseAddr   The pointer to caller allocated space to return the\r
+                                I/O port base addresses of the IDE and SATA channels\r
                                 that were previosuly enabled with EnableAtaChannel().\r
 \r
   @return   The number of enabled IDE and SATA channels in the platform.\r
@@ -143,7 +143,7 @@ UINT32
 (EFIAPI *GET_IDE_REGS_BASE_ADDR)(\r
   IN  EFI_PEI_SERVICES        **PeiServices,\r
   IN  PEI_ATA_CONTROLLER_PPI  *This,\r
-  OUT IDE_REGS_BASE_ADDR      *IdeRegsBaseAddr \r
+  OUT IDE_REGS_BASE_ADDR      *IdeRegsBaseAddr\r
   );\r
 \r
 ///\r