It abstracts the location and characteristics of SMRAM. The expectation is\r
that the north bridge or memory controller would publish this PPI.\r
\r
- The principal functionality found in the memory controller includes the following: \r
+ The principal functionality found in the memory controller includes the following:\r
- Exposing the SMRAM to all non-SMM agents, or the "open" state\r
- Shrouding the SMRAM to all but the SMM agents, or the "closed" state\r
- - Preserving the system integrity, or "locking" the SMRAM, such that the settings cannot be \r
- perturbed by either boot service or runtime agents \r
+ - Preserving the system integrity, or "locking" the SMRAM, such that the settings cannot be\r
+ perturbed by either boot service or runtime agents\r
\r
-Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
/**\r
Opens the SMRAM area to be accessible by a PEIM driver.\r
\r
- This function "opens" SMRAM so that it is visible while not inside of SMM. The function should \r
- return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM. The function \r
+ This function "opens" SMRAM so that it is visible while not inside of SMM. The function should\r
+ return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM. The function\r
should return EFI_DEVICE_ERROR if the SMRAM configuration is locked.\r
\r
@param PeiServices General purpose services available to every PEIM.\r
@param This The pointer to the SMM Access Interface.\r
@param DescriptorIndex The region of SMRAM to Open.\r
- \r
+\r
@retval EFI_SUCCESS The region was successfully opened.\r
@retval EFI_DEVICE_ERROR The region could not be opened because locked by chipset.\r
@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
- \r
+\r
**/\r
typedef\r
EFI_STATUS\r
/**\r
Inhibits access to the SMRAM.\r
\r
- This function "closes" SMRAM so that it is not visible while outside of SMM. The function should \r
+ This function "closes" SMRAM so that it is not visible while outside of SMM. The function should\r
return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM.\r
\r
@param PeiServices General purpose services available to every PEIM.\r
@param This The pointer to the SMM Access Interface.\r
@param DescriptorIndex The region of SMRAM to Close.\r
- \r
+\r
@retval EFI_SUCCESS The region was successfully closed.\r
- @retval EFI_DEVICE_ERROR The region could not be closed because locked by chipset. \r
+ @retval EFI_DEVICE_ERROR The region could not be closed because locked by chipset.\r
@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
\r
**/\r
/**\r
Inhibits access to the SMRAM.\r
\r
- This function prohibits access to the SMRAM region. This function is usually implemented such \r
- that it is a write-once operation. \r
+ This function prohibits access to the SMRAM region. This function is usually implemented such\r
+ that it is a write-once operation.\r
\r
@param PeiServices General purpose services available to every PEIM.\r
@param This The pointer to the SMM Access Interface.\r
@param DescriptorIndex The region of SMRAM to Close.\r
- \r
+\r
@retval EFI_SUCCESS The region was successfully locked.\r
@retval EFI_DEVICE_ERROR The region could not be locked because at least\r
one range is still open.\r
buffer to contain the description information.\r
@param SmramMap The buffer containing the data describing the Smram\r
region descriptors.\r
- \r
+\r
@retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.\r
@retval EFI_SUCCESS The user provided a sufficiently-sized buffer.\r
\r
\r
///\r
/// EFI SMM Access PPI is used to control the visibility of the SMRAM on the platform.\r
-/// It abstracts the location and characteristics of SMRAM. The platform should report \r
-/// all MMRAM via PEI_SMM_ACCESS_PPI. The expectation is that the north bridge or \r
+/// It abstracts the location and characteristics of SMRAM. The platform should report\r
+/// all MMRAM via PEI_SMM_ACCESS_PPI. The expectation is that the north bridge or\r
/// memory controller would publish this PPI.\r
-/// \r
+///\r
struct _PEI_SMM_ACCESS_PPI {\r
PEI_SMM_OPEN Open;\r
PEI_SMM_CLOSE Close;\r