# @Prompt Enable S3 performance data support.\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|TRUE|BOOLEAN|0x00010064\r
\r
+ ## Indicates if Serial device uses half hand shake.<BR><BR>\r
+ # TRUE - Serial device uses half hand shake.<BR>\r
+ # FALSE - Serial device doesn't use half hand shake.<BR>\r
+ # @Prompt Enable Serial device Half Hand Shake\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHalfHandshake|FALSE|BOOLEAN|0x00010073\r
+\r
[PcdsFeatureFlag.IA32, PcdsFeatureFlag.X64]\r
## Indicates if DxeIpl should switch to long mode to enter DXE phase.\r
# It is assumed that 64-bit DxeCore is built in firmware if it is true; otherwise 32-bit DxeCore\r
# @Prompt Pci Serial Device Info\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF}|VOID*|0x00010067\r
\r
+ ## PCI Serial Parameters. It is an array of VendorID, DeviceID, ClockRate, Offset,\r
+ # BarIndex, RegisterStride, ReceiveFifoDepth, TransmitFifoDepth information that \r
+ # describes the parameters of special PCI serial devices.\r
+ # Each array entry is 24-byte in length. The array is terminated\r
+ # by an array entry with a PCI Vendor ID of 0xFFFF. If a platform only contains a\r
+ # standard 16550 PCI serial device whose class code is 7/0/2, the value is 0xFFFF.\r
+ # The C style structure is defined as below:\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ # It contains zero or more instances of the above structure.\r
+ # For example, if a PCI device contains two UARTs, PcdPciSerialParameters needs\r
+ # to contain two instances of the above structure, with the VendorId and DeviceId\r
+ # equals to the Device ID and Vendor ID of the device; If the PCI device uses the\r
+ # first two BARs to support two UARTs, BarIndex of first instance equals to 0 and\r
+ # BarIndex of second one equals to 1; If the PCI device uses the first BAR to\r
+ # support both UARTs, BarIndex of both instance equals to 0, Offset of first\r
+ # instance equals to 0 and Offset of second one equals to a value bigger than or\r
+ # equal to 8.\r
+ # For certain UART whose register needs to be accessed in DWORD aligned address,\r
+ # RegisterStride equals to 4.\r
+ # @Prompt Pci Serial Parameters\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0xFF, 0xFF}|VOID*|0x00010071\r
+\r
## Serial Port Extended Transmit FIFO Size. The default is 64 bytes. \r
# @Prompt Serial Port Extended Transmit FIFO Size in Bytes\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|64|UINT32|0x00010068\r