-//++\r
-// Copyright (c) 2006, Intel Corporation \r
-// All rights reserved. This program and the accompanying materials \r
-// are licensed and made available under the terms and conditions of the BSD License \r
-// which accompanies this distribution. The full text of the license may be found at \r
-// http://opensource.org/licenses/bsd-license.php \r
-// \r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-// \r
-// Module Name:\r
-//\r
-// AsmFuncs.s\r
-//\r
-// Abstract:\r
-//\r
-// Low level IPF routines used by the debug support driver\r
-//\r
-// Revision History:\r
-//\r
-//--\r
+/// @file\r
+/// Low level IPF routines used by the debug support driver\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution. The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: AsmFuncs.s\r
+///\r
+///\r
\r
\r
#include "common.i"\r
// our chained handler installed:\r
//\r
//\r
-// \r
-// \r
-// \r
-// This IVT entry is Failsafe bundle \r
-// reserved by the \r
-// Itanium architecture Original bundle 0 \r
-// and is used for \r
-// for locating our \r
-// handler and the \r
-// original bundle Patch code... \r
-// zero of the ext \r
-// interrupt handler \r
-// \r
-// RSVD (3400) Unused \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
-// \r
+//\r
+//\r
+//\r
+// This IVT entry is Failsafe bundle\r
+// reserved by the\r
+// Itanium architecture Original bundle 0\r
+// and is used for\r
+// for locating our\r
+// handler and the\r
+// original bundle Patch code...\r
+// zero of the ext\r
+// interrupt handler\r
+//\r
+// RSVD (3400) Unused\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
+//\r
// EXT_INT (3000) Bundle 0 Bundle zero - This one is\r
// modified, all other bundles\r
// in the EXT_INT entry are\r
add loc3=loc2, in1;; // loc3 = physical address of branch target\r
(p14) sub loc2=r0,loc2;; // flip sign in loc2 if offset is negative\r
sub loc4=loc3,in2;; // loc4 = relative offset from new ip to branch target\r
- cmp.lt p15, p14 = 0, loc4;; // get new sign bit \r
+ cmp.lt p15, p14 = 0, loc4;; // get new sign bit\r
(p14) sub loc5=r0,loc4 // get absolute value of offset\r
(p15) mov loc5=loc4;;\r
movl loc6=0x0FFFFFF;; // maximum offset in bytes for ip-rel branch\r
// the backing store. The processor, however may not be aware that the\r
// stacked registers need to be reloaded from the backing store. Therefore,\r
// we explicitly cause the RSE to refresh the stacked register's contents\r
- // from the backing store. \r
+ // from the backing store.\r
mov loc0=ar.rsc // get RSC value\r
mov loc1=ar.rsc // save it so we can restore it\r
movl loc3=0xffffffffc000ffff;; // create mask for clearing RSC.loadrs\r
movl SCRATCH_REG1 = ~( MASK(PSR_DT,1) | MASK(PSR_RT,1));;\r
and SCRATCH_REG1 = SCRATCH_REG0, SCRATCH_REG1;;\r
mov psr.l = SCRATCH_REG1;;\r
- srlz.d \r
+ srlz.d\r
tbit.z p14, p15 = SCRATCH_REG6, PSR_IS;; // Check to see if we were\r
// interrupted from IA32\r
// context. If so, bail out\r