//\r
// Large Item Descriptor Name\r
//\r
-#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D\r
-#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F\r
-#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10\r
-#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11\r
-#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12\r
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D\r
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F\r
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10\r
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11\r
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12\r
\r
//\r
// Large Item Descriptor Value\r
//\r
-#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D\r
-#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F\r
-#define ACPI_PIN_GROUP_DESCRIPTOR 0x90\r
-#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91\r
-#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92\r
+#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D\r
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F\r
+#define ACPI_PIN_GROUP_DESCRIPTOR 0x90\r
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91\r
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92\r
\r
#pragma pack(1)\r
\r
/// ACPI 6.2 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
-#define EFI_ACPI_6_2_SYSTEM_MEMORY 0\r
-#define EFI_ACPI_6_2_SYSTEM_IO 1\r
-#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2\r
-#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3\r
-#define EFI_ACPI_6_2_SMBUS 4\r
+#define EFI_ACPI_6_2_SYSTEM_MEMORY 0\r
+#define EFI_ACPI_6_2_SYSTEM_IO 1\r
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2\r
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3\r
+#define EFI_ACPI_6_2_SMBUS 4\r
#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A\r
#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F\r
\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2\r
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_2_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
- UINT64 HypervisorVendorIdentity;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ UINT64 HypervisorVendorIdentity;\r
} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_6_2_8042 BIT1\r
-#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_6_2_8042 BIT1\r
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_2_WBINVD BIT0\r
-#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_6_2_PROC_C1 BIT2\r
-#define EFI_ACPI_6_2_P_LVL2_UP BIT3\r
-#define EFI_ACPI_6_2_PWR_BUTTON BIT4\r
-#define EFI_ACPI_6_2_SLP_BUTTON BIT5\r
-#define EFI_ACPI_6_2_FIX_RTC BIT6\r
-#define EFI_ACPI_6_2_RTC_S4 BIT7\r
-#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_6_2_DCK_CAP BIT9\r
-#define EFI_ACPI_6_2_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_6_2_SEALED_CASE BIT11\r
-#define EFI_ACPI_6_2_HEADLESS BIT12\r
-#define EFI_ACPI_6_2_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_6_2_WBINVD BIT0\r
+#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_6_2_PROC_C1 BIT2\r
+#define EFI_ACPI_6_2_P_LVL2_UP BIT3\r
+#define EFI_ACPI_6_2_PWR_BUTTON BIT4\r
+#define EFI_ACPI_6_2_SLP_BUTTON BIT5\r
+#define EFI_ACPI_6_2_FIX_RTC BIT6\r
+#define EFI_ACPI_6_2_RTC_S4 BIT7\r
+#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_6_2_DCK_CAP BIT9\r
+#define EFI_ACPI_6_2_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_6_2_SEALED_CASE BIT11\r
+#define EFI_ACPI_6_2_HEADLESS BIT12\r
+#define EFI_ACPI_6_2_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_S4BIOS_F BIT0\r
-#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_6_2_S4BIOS_F BIT0\r
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_6_2_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_6_2_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
- UINT8 ProcessorPowerEfficiencyClass;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_2_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GIC_ENABLED BIT0\r
-#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_6_2_GIC_ENABLED BIT0\r
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_6_2_GIC_V1 0x01\r
-#define EFI_ACPI_6_2_GIC_V2 0x02\r
-#define EFI_ACPI_6_2_GIC_V3 0x03\r
-#define EFI_ACPI_6_2_GIC_V4 0x04\r
+#define EFI_ACPI_6_2_GIC_V1 0x01\r
+#define EFI_ACPI_6_2_GIC_V2 0x02\r
+#define EFI_ACPI_6_2_GIC_V3 0x03\r
+#define EFI_ACPI_6_2_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_6_2_GICR_STRUCTURE;\r
\r
///\r
/// GIC Interrupt Translation Service Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicItsId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicItsId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)\r
\r
///\r
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT8 Reserved[2];\r
- UINT32 ItsId;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT8 Reserved[2];\r
+ UINT32 ItsId;\r
} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;\r
\r
///\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_6_2_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI RASF Platform RAS Capabilities\r
///\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_6_2_BGRT_VERSION 0x01\r
+#define EFI_ACPI_6_2_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// SBSA Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
//\r
// NVDIMM Firmware Interface Table definition.\r
//\r
// NFIT Version (as defined in ACPI 6.2 spec.)\r
//\r
-#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
\r
//\r
// Definition for NFIT Table Structure Types\r
//\r
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
-#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
-#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
-#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
\r
//\r
// Definition for NFIT Structure Header\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;\r
\r
//\r
// Definition for System Physical Address Range Structure\r
//\r
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
-#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 SPARangeStructureIndex;\r
- UINT16 Flags;\r
- UINT32 Reserved_8;\r
- UINT32 ProximityDomain;\r
- GUID AddressRangeTypeGUID;\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
- UINT64 AddressRangeMemoryMappingAttribute;\r
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 Flags;\r
+ UINT32 Reserved_8;\r
+ UINT32 ProximityDomain;\r
+ GUID AddressRangeTypeGUID;\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT64 AddressRangeMemoryMappingAttribute;\r
} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\r
\r
//\r
// Definition for Memory Device to System Physical Address Range Mapping Structure\r
//\r
typedef struct {\r
- UINT32 DIMMNumber:4;\r
- UINT32 MemoryChannelNumber:4;\r
- UINT32 MemoryControllerID:4;\r
- UINT32 SocketID:4;\r
- UINT32 NodeControllerID:12;\r
- UINT32 Reserved_28:4;\r
+ UINT32 DIMMNumber : 4;\r
+ UINT32 MemoryChannelNumber : 4;\r
+ UINT32 MemoryControllerID : 4;\r
+ UINT32 SocketID : 4;\r
+ UINT32 NodeControllerID : 12;\r
+ UINT32 Reserved_28 : 4;\r
} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;\r
\r
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\r
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\r
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NVDIMMPhysicalID;\r
- UINT16 NVDIMMRegionID;\r
- UINT16 SPARangeStructureIndex ;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT64 NVDIMMRegionSize;\r
- UINT64 RegionOffset;\r
- UINT64 NVDIMMPhysicalAddressRegionBase;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 InterleaveWays;\r
- UINT16 NVDIMMStateFlags;\r
- UINT16 Reserved_46;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NVDIMMPhysicalID;\r
+ UINT16 NVDIMMRegionID;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT64 NVDIMMRegionSize;\r
+ UINT64 RegionOffset;\r
+ UINT64 NVDIMMPhysicalAddressRegionBase;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 InterleaveWays;\r
+ UINT16 NVDIMMStateFlags;\r
+ UINT16 Reserved_46;\r
} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\r
\r
//\r
// Definition for Interleave Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 Reserved_6;\r
- UINT32 NumberOfLines;\r
- UINT32 LineSize;\r
-//UINT32 LineOffset[NumberOfLines];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 Reserved_6;\r
+ UINT32 NumberOfLines;\r
+ UINT32 LineSize;\r
+ // UINT32 LineOffset[NumberOfLines];\r
} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;\r
\r
//\r
// Definition for SMBIOS Management Information Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT32 Reserved_4;\r
-//UINT8 Data[];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT32 Reserved_4;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Control Region Structure\r
//\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
-\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 VendorID;\r
- UINT16 DeviceID;\r
- UINT16 RevisionID;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemDeviceID;\r
- UINT16 SubsystemRevisionID;\r
- UINT8 ValidFields;\r
- UINT8 ManufacturingLocation;\r
- UINT16 ManufacturingDate;\r
- UINT8 Reserved_22[2];\r
- UINT32 SerialNumber;\r
- UINT16 RegionFormatInterfaceCode;\r
- UINT16 NumberOfBlockControlWindows;\r
- UINT64 SizeOfBlockControlWindow;\r
- UINT64 CommandRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
- UINT64 StatusRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
- UINT16 NVDIMMControlRegionFlag;\r
- UINT8 Reserved_74[6];\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
+\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevisionID;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemDeviceID;\r
+ UINT16 SubsystemRevisionID;\r
+ UINT8 ValidFields;\r
+ UINT8 ManufacturingLocation;\r
+ UINT16 ManufacturingDate;\r
+ UINT8 Reserved_22[2];\r
+ UINT32 SerialNumber;\r
+ UINT16 RegionFormatInterfaceCode;\r
+ UINT16 NumberOfBlockControlWindows;\r
+ UINT64 SizeOfBlockControlWindow;\r
+ UINT64 CommandRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
+ UINT64 StatusRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
+ UINT16 NVDIMMControlRegionFlag;\r
+ UINT8 Reserved_74[6];\r
} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Block Data Window Region Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 NumberOfBlockDataWindows;\r
- UINT64 BlockDataWindowStartOffset;\r
- UINT64 SizeOfBlockDataWindow;\r
- UINT64 BlockAccessibleMemoryCapacity;\r
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 NumberOfBlockDataWindows;\r
+ UINT64 BlockDataWindowStartOffset;\r
+ UINT64 SizeOfBlockDataWindow;\r
+ UINT64 BlockAccessibleMemoryCapacity;\r
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\r
\r
//\r
// Definition for Flush Hint Address Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NumberOfFlushHintAddresses;\r
- UINT8 Reserved_10[6];\r
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NumberOfFlushHintAddresses;\r
+ UINT8 Reserved_10[6];\r
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
///\r
/// Secure DEVices Table (SDEV)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;\r
\r
///\r
/// SDEV Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01\r
\r
///\r
/// Secure Device types\r
///\r
-#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
-#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
\r
///\r
/// Secure Device flags\r
///\r
-#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
\r
///\r
/// SDEV Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;\r
\r
///\r
/// PCIe Endpoint Device based Secure Device Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
- UINT16 PciSegmentNumber;\r
- UINT16 StartBusNumber;\r
- UINT16 PciPathOffset;\r
- UINT16 PciPathLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
+ UINT16 PciSegmentNumber;\r
+ UINT16 StartBusNumber;\r
+ UINT16 PciPathOffset;\r
+ UINT16 PciPathLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\r
\r
///\r
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
- UINT16 DeviceIdentifierOffset;\r
- UINT16 DeviceIdentifierLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
+ UINT16 DeviceIdentifierOffset;\r
+ UINT16 DeviceIdentifierLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
- UINT8 Timestamp[8];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
+ UINT8 Timestamp[8];\r
} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Version 2 Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
- UINT64 ReadAckPreserve;\r
- UINT64 ReadAckWrite;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
+ UINT64 ReadAckPreserve;\r
+ UINT64 ReadAckWrite;\r
} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
UINT8 NumberOfHardwareBanks;\r
UINT8 Reserved1[3];\r
-} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;\r
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// HMAT - Heterogeneous Memory Attribute Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[4];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\r
\r
///\r
/// HMAT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01\r
\r
///\r
/// HMAT types\r
///\r
-#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00\r
-#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
-#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00\r
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
\r
///\r
/// HMAT Structure Header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;\r
\r
///\r
/// Memory Subsystem Address Range Structure flags\r
///\r
typedef struct {\r
- UINT16 ProcessorProximityDomainValid:1;\r
- UINT16 MemoryProximityDomainValid:1;\r
- UINT16 ReservationHint:1;\r
- UINT16 Reserved:13;\r
+ UINT16 ProcessorProximityDomainValid : 1;\r
+ UINT16 MemoryProximityDomainValid : 1;\r
+ UINT16 ReservationHint : 1;\r
+ UINT16 Reserved : 13;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;\r
\r
///\r
/// Memory Subsystem Address Range Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;\r
- UINT8 Reserved1[2];\r
- UINT32 ProcessorProximityDomain;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved2[4];\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProcessorProximityDomain;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved2[4];\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure flags\r
///\r
typedef struct {\r
- UINT8 MemoryHierarchy:5;\r
- UINT8 Reserved:3;\r
+ UINT8 MemoryHierarchy : 5;\r
+ UINT8 Reserved : 3;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
- UINT8 DataType;\r
- UINT8 Reserved1[2];\r
- UINT32 NumberOfInitiatorProximityDomains;\r
- UINT32 NumberOfTargetProximityDomains;\r
- UINT8 Reserved2[4];\r
- UINT64 EntryBaseUnit;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
+ UINT8 DataType;\r
+ UINT8 Reserved1[2];\r
+ UINT32 NumberOfInitiatorProximityDomains;\r
+ UINT32 NumberOfTargetProximityDomains;\r
+ UINT8 Reserved2[4];\r
+ UINT64 EntryBaseUnit;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\r
\r
///\r
/// Memory Side Cache Information Structure cache attributes\r
///\r
typedef struct {\r
- UINT32 TotalCacheLevels:4;\r
- UINT32 CacheLevel:4;\r
- UINT32 CacheAssociativity:4;\r
- UINT32 WritePolicy:4;\r
- UINT32 CacheLineSize:16;\r
+ UINT32 TotalCacheLevels : 4;\r
+ UINT32 CacheLevel : 4;\r
+ UINT32 CacheAssociativity : 4;\r
+ UINT32 WritePolicy : 4;\r
+ UINT32 CacheLineSize : 16;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\r
\r
///\r
/// Memory Side Cache Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved1[4];\r
- UINT64 MemorySideCacheSize;\r
- EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
- UINT8 Reserved2[2];\r
- UINT16 NumberOfSmbiosHandles;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved1[4];\r
+ UINT64 MemorySideCacheSize;\r
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
+ UINT8 Reserved2[2];\r
+ UINT16 NumberOfSmbiosHandles;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
-#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_2_ERST_NOOP 0x04\r
-#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_6_2_ERST_ADD 0x08\r
-#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_6_2_ERST_STALL 0x0C\r
-#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_6_2_ERST_GOTO 0x0F\r
-#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_2_ERST_NOOP 0x04\r
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_6_2_ERST_ADD 0x08\r
+#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_6_2_ERST_STALL 0x0C\r
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_6_2_ERST_GOTO 0x0F\r
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_2_EINJ_NOOP 0x04\r
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_2_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
\r
///\r
/// PCCT Global Flags\r
//\r
// PCCT Subspace type\r
//\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 NotifyOnCompletion:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 NotifyOnCompletion : 1;\r
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 PlatformInterrupt:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 PlatformInterrupt : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\r
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
\r
///\r
/// Type 1 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 2 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckWrite;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckWrite;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 3 Extended PCC Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT32 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT32 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckSet;\r
- UINT8 Reserved1[8];\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
- UINT64 CommandCompleteCheckMask;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
- UINT64 CommandCompleteUpdatePreserve;\r
- UINT64 CommandCompleteUpdateSet;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
- UINT64 ErrorStatusMask;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT32 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT32 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckSet;\r
+ UINT8 Reserved1[8];\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
+ UINT64 CommandCompleteCheckMask;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
+ UINT64 CommandCompleteUpdatePreserve;\r
+ UINT64 CommandCompleteUpdateSet;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
+ UINT64 ErrorStatusMask;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;\r
\r
///\r
///\r
typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;\r
\r
-#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Flags;\r
- UINT32 Length;\r
- UINT32 Command;\r
+ UINT32 Signature;\r
+ UINT32 Flags;\r
+ UINT32 Length;\r
+ UINT32 Command;\r
} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\r
\r
///\r
/// Platform Debug Trigger Table (PDTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 TriggerCount;\r
- UINT8 Reserved[3];\r
- UINT32 TriggerIdentifierArrayOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 TriggerCount;\r
+ UINT8 Reserved[3];\r
+ UINT32 TriggerIdentifierArrayOffset;\r
} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\r
\r
///\r
/// PDTT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
\r
///\r
/// PDTT Platform Communication Channel Identifier Structure\r
///\r
typedef struct {\r
- UINT16 SubChannelIdentifer:8;\r
- UINT16 Runtime:1;\r
- UINT16 WaitForCompletion:1;\r
- UINT16 Reserved:6;\r
+ UINT16 SubChannelIdentifer : 8;\r
+ UINT16 Runtime : 1;\r
+ UINT16 WaitForCompletion : 1;\r
+ UINT16 Reserved : 6;\r
} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;\r
\r
///\r
/// PCC Commands Codes used by Platform Debug Trigger Table\r
///\r
-#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
-#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
\r
///\r
/// PPTT Platform Communication Channel\r
/// Processor Properties Topology Table (PPTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\r
\r
///\r
/// PPTT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// PPTT types\r
///\r
-#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00\r
-#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01\r
-#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02\r
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00\r
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01\r
+#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02\r
\r
///\r
/// PPTT Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;\r
\r
///\r
/// For PPTT struct processor flags\r
///\r
-#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0\r
-#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1\r
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0\r
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1\r
\r
///\r
/// Processor hierarchy node structure flags\r
///\r
typedef struct {\r
- UINT32 PhysicalPackage:1;\r
- UINT32 AcpiProcessorIdValid:1;\r
- UINT32 Reserved:30;\r
+ UINT32 PhysicalPackage : 1;\r
+ UINT32 AcpiProcessorIdValid : 1;\r
+ UINT32 Reserved : 30;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;\r
\r
///\r
/// Processor hierarchy node structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
- UINT32 Parent;\r
- UINT32 AcpiProcessorId;\r
- UINT32 NumberOfPrivateResources;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
+ UINT32 Parent;\r
+ UINT32 AcpiProcessorId;\r
+ UINT32 NumberOfPrivateResources;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;\r
\r
///\r
/// Cache Type Structure flags\r
///\r
typedef struct {\r
- UINT32 SizePropertyValid:1;\r
- UINT32 NumberOfSetsValid:1;\r
- UINT32 AssociativityValid:1;\r
- UINT32 AllocationTypeValid:1;\r
- UINT32 CacheTypeValid:1;\r
- UINT32 WritePolicyValid:1;\r
- UINT32 LineSizeValid:1;\r
- UINT32 Reserved:25;\r
+ UINT32 SizePropertyValid : 1;\r
+ UINT32 NumberOfSetsValid : 1;\r
+ UINT32 AssociativityValid : 1;\r
+ UINT32 AllocationTypeValid : 1;\r
+ UINT32 CacheTypeValid : 1;\r
+ UINT32 WritePolicyValid : 1;\r
+ UINT32 LineSizeValid : 1;\r
+ UINT32 Reserved : 25;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;\r
\r
///\r
/// For cache attributes\r
///\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
\r
///\r
/// Cache Type Structure cache attributes\r
///\r
typedef struct {\r
- UINT8 AllocationType:2;\r
- UINT8 CacheType:2;\r
- UINT8 WritePolicy:1;\r
- UINT8 Reserved:3;\r
+ UINT8 AllocationType : 2;\r
+ UINT8 CacheType : 2;\r
+ UINT8 WritePolicy : 1;\r
+ UINT8 Reserved : 3;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\r
\r
///\r
/// Cache Type Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
- UINT32 NextLevelOfCache;\r
- UINT32 Size;\r
- UINT32 NumberOfSets;\r
- UINT8 Associativity;\r
- EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
- UINT16 LineSize;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
+ UINT32 NextLevelOfCache;\r
+ UINT32 Size;\r
+ UINT32 NumberOfSets;\r
+ UINT8 Associativity;\r
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
+ UINT16 LineSize;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;\r
\r
///\r
/// ID structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 VendorId;\r
- UINT64 Level1Id;\r
- UINT64 Level2Id;\r
- UINT16 MajorRev;\r
- UINT16 MinorRev;\r
- UINT16 SpinRev;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 VendorId;\r
+ UINT64 Level1Id;\r
+ UINT64 Level2Id;\r
+ UINT16 MajorRev;\r
+ UINT16 MinorRev;\r
+ UINT16 SpinRev;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;\r
\r
//\r
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