Definitions based on NVMe spec. version 1.1.\r
\r
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
@par Specification Reference:\r
NVMe Specification 1.1\r
+ NVMe Specification 1.4\r
\r
**/\r
\r
//\r
// controller register offsets\r
//\r
-#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
-#define NVME_VER_OFFSET 0x0008 // Version\r
-#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
-#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
-#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
-#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
-#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
-#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
-#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
-#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
-#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
-#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
+#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
+#define NVME_VER_OFFSET 0x0008 // Version\r
+#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
+#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
+#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
+#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
+#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
+#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
+#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
+#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information\r
+#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select\r
+#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location\r
+#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
+#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
\r
//\r
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
UINT8 To; // Timeout\r
UINT16 Dstrd : 4;\r
UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS\r
- UINT16 Css : 4; // Command Sets Supported - Bit 37\r
- UINT16 Rsvd3 : 7;\r
+ UINT16 Css : 8; // Command Sets Supported - Bit 37\r
+ UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4\r
+ UINT16 Rsvd3 : 2;\r
UINT8 Mpsmin : 4;\r
UINT8 Mpsmax : 4;\r
- UINT8 Rsvd4;\r
+ UINT8 Pmrs : 1;\r
+ UINT8 Cmbs : 1;\r
+ UINT8 Rsvd4 : 6;\r
} NVME_CAP;\r
\r
//\r
#define NVME_ACQ UINT64\r
\r
//\r
-// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
+// 3.1.13 Offset 40h: BPINFO - Boot Partition Information\r
+//\r
+typedef struct {\r
+ UINT32 Bpsz : 15; // Boot Partition Size\r
+ UINT32 Rsvd1 : 9;\r
+ UINT32 Brs : 2; // Boot Read Status\r
+ UINT32 Rsvd2 : 5;\r
+ UINT32 Abpid : 1; // Active Boot Partition ID\r
+} NVME_BPINFO;\r
+\r
+//\r
+// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select\r
+//\r
+typedef struct {\r
+ UINT32 Bprsz : 10; // Boot Partition Read Size\r
+ UINT32 Bprof : 20; // Boot Partition Read Offset\r
+ UINT32 Rsvd1 : 1;\r
+ UINT32 Bpid : 1; // Boot Partition Identifier\r
+} NVME_BPRSEL;\r
+\r
+//\r
+// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)\r
+//\r
+typedef struct {\r
+ UINT64 Rsvd1 : 12;\r
+ UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address\r
+} NVME_BPMBL;\r
+\r
+//\r
+// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
//\r
typedef struct {\r
UINT16 Sqt;\r
UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
//\r
- // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec\r
+ // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec\r
//\r
UINT16 Wctemp; /* Warning Composite Temperature Threshold */\r
UINT16 Cctemp; /* Critical Composite Temperature Threshold */\r
UINT32 Hmpre; /* Host Memory Buffer Preferred Size */\r
UINT32 Hmmin; /* Host Memory Buffer Minimum Size */\r
UINT8 Tnvmcap[16]; /* Total NVM Capacity */\r
- UINT8 Rsvd2[216]; /* Reserved as of NVM Express */\r
+ UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */\r
+ UINT32 Rpmbs; /* Replay Protected Memory Block Support */\r
+ UINT16 Edstt; /* Extended Device Self-test Time */\r
+ UINT8 Dsto; /* Device Self-test Options */\r
+ UINT8 Fwug; /* Firmware Update Granularity */\r
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec */\r
//\r
// NVM Command Set Attributes\r
//\r
UINT8 VendorData[3712]; /* Vendor specific data */\r
} NVME_ADMIN_NAMESPACE_DATA;\r
\r
+//\r
+// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec\r
+//\r
+typedef struct {\r
+ UINT8 Bppe; /* Boot Partition Protection Enable */\r
+ UINT8 Bpl; /* Boot Partition Lock */\r
+ UINT8 Nwpac; /* Namespace Write Protection Authentication Control */\r
+ UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */\r
+} NVME_RPMB_CONFIGURATION_DATA;\r
+\r
+#define RPMB_FRAME_STUFF_BYTES 223\r
+\r
+//\r
+// RPMB Data Frame as of Nvm Express 1.4 Spec\r
+//\r
+typedef struct {\r
+ UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */\r
+ /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */\r
+ UINT8 Rpmbt; /* RPMB Target */\r
+ UINT64 Nonce[2];\r
+ UINT32 Wcounter; /* Write Counter */\r
+ UINT32 Address; /* Starting address of data to be programmed to or read from the RPMB. */\r
+ UINT32 Scount; /* Sector Count */\r
+ UINT16 Result;\r
+ UINT16 Rpmessage; /* Request/Response Message */\r
+ // UINT8 *Data; /* Data to be written or read by signed access where M = 512 * Sector Count. */\r
+} NVME_RPMB_DATA_FRAME;\r
+\r
//\r
// NvmExpress Admin Identify Cmd\r
//\r
#define LID_ERROR_INFO 0x1\r
#define LID_SMART_INFO 0x2\r
#define LID_FW_SLOT_INFO 0x3\r
+ #define LID_BP_INFO 0x15\r
UINT32 Rsvd1 : 8;\r
UINT32 Numd : 12; /* Number of Dwords */\r
UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */\r
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