Definitions based on NVMe spec. version 1.1.\r
\r
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
UINT8 Rsvd2;\r
} NVME_CC;\r
+#define NVME_CC_SHN_NORMAL_SHUTDOWN 1\r
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2\r
\r
//\r
// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
UINT32 Rsvd1:27;\r
} NVME_CSTS;\r
-\r
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1\r
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2\r
//\r
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
//\r