MdePkg/Pci22.h: Remove deprecated macros

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 4a191403e3bff14ec08069fc4024e5ec9e398eeb..96a76801d3e95166abfe6142aecef4ba938e6fe5 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -5,11 +5,10 @@
     PCI Local Bus Specification, 2.2\r
     PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
     PC Card Standard, 8.0\r
+    PCI Power Management Interface Specifiction, Revision 1.2\r
 \r
-  \r
-\r
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
-  Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>\r
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
   This program and the accompanying materials                          \r
   are licensed and made available under the terms and conditions of the BSD License         \r
   which accompanies this distribution.  The full text of the license may be found at        \r
@@ -552,6 +551,7 @@ typedef struct {
 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   \r
 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   \r
 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   \r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   \r
 \r
@@ -635,6 +635,7 @@ typedef union {
 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04\r
 #define EFI_PCI_CAPABILITY_ID_MSI     0x05\r
 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_SHPC    0x0C\r
 \r
 ///\r
 /// Capabilities List Header\r
@@ -645,18 +646,6 @@ typedef struct {
   UINT8 NextItemPtr;\r
 } EFI_PCI_CAPABILITY_HDR;\r
 \r
-///\r
-/// Power Management Register Block Definition \r
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
-///\r
-typedef struct {\r
-  EFI_PCI_CAPABILITY_HDR  Hdr;\r
-  UINT16                  PMC;\r
-  UINT16                  PMCSR;\r
-  UINT8                   BridgeExtention;\r
-  UINT8                   Data;\r
-} EFI_PCI_CAPABILITY_PMI;\r
-\r
 ///\r
 /// PMC - Power Management Capabilities\r
 /// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
@@ -665,7 +654,7 @@ typedef union {
   struct {\r
     UINT16 Version : 3;\r
     UINT16 PmeClock : 1;\r
-    UINT16 : 1;\r
+    UINT16 Reserved : 1;\r
     UINT16 DeviceSpecificInitialization : 1;\r
     UINT16 AuxCurrent : 3;\r
     UINT16 D1Support : 1;\r
@@ -684,7 +673,9 @@ typedef union {
 typedef union {\r
   struct {\r
     UINT16 PowerState : 2;\r
-    UINT16 : 6;\r
+    UINT16 ReservedForPciExpress : 1;\r
+    UINT16 NoSoftReset : 1;\r
+    UINT16 Reserved : 4;\r
     UINT16 PmeEnable : 1;\r
     UINT16 DataSelect : 4;\r
     UINT16 DataScale : 2;\r
@@ -693,6 +684,36 @@ typedef union {
   UINT16 Data;\r
 } EFI_PCI_PMCSR;\r
 \r
+#define PCI_POWER_STATE_D0     0\r
+#define PCI_POWER_STATE_D1     1\r
+#define PCI_POWER_STATE_D2     2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+  struct {\r
+    UINT8 Reserved : 6;\r
+    UINT8 B2B3 : 1;\r
+    UINT8 BusPowerClockControl : 1;\r
+  } Bits;\r
+  UINT8   Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef struct {\r
+  EFI_PCI_CAPABILITY_HDR  Hdr;\r
+  EFI_PCI_PMC             PMC;\r
+  EFI_PCI_PMCSR           PMCSR;\r
+  EFI_PCI_PMCSR_BSE       BridgeExtention;\r
+  UINT8                   Data;\r
+} EFI_PCI_CAPABILITY_PMI;\r
+\r
 ///\r
 /// A.G.P Capability\r
 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
@@ -759,22 +780,12 @@ typedef struct {
   ///\r
 } EFI_PCI_CAPABILITY_HOTPLUG;\r
 \r
-#define DEVICE_ID_NOCARE    0xFFFF\r
-\r
-#define PCI_ACPI_UNUSED     0\r
-#define PCI_BAR_NOCHANGE    0\r
-#define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL\r
-#define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL\r
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
-\r
 #define PCI_BAR_IDX0        0x00\r
 #define PCI_BAR_IDX1        0x01\r
 #define PCI_BAR_IDX2        0x02\r
 #define PCI_BAR_IDX3        0x03\r
 #define PCI_BAR_IDX4        0x04\r
 #define PCI_BAR_IDX5        0x05\r
-#define PCI_BAR_ALL         0xFF\r
 \r
 ///\r
 /// EFI PCI Option ROM definitions\r