PCI Local Bus Specification, 2.2\r
PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
PC Card Standard, 8.0\r
+ PCI Power Management Interface Specifiction, Revision 1.2\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
#ifndef _PCI22_H_\r
#define _PCI22_H_\r
\r
-#define PCI_MAX_SEGMENT 0\r
#define PCI_MAX_BUS 255\r
#define PCI_MAX_DEVICE 31\r
#define PCI_MAX_FUNC 7\r
#define PCI_IF_16550_MODEM 0x02\r
#define PCI_IF_16650_MODEM 0x03\r
#define PCI_IF_16750_MODEM 0x04\r
-#define PCI_SUBCLASS_SCC_OTHER 0x80\r
+#define PCI_SUBCLASS_SCC_OTHER 0x80\r
\r
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
#define PCI_SUBCLASS_PIC 0x00\r
#define PCI_IF_EISA_TIMER 0x02\r
#define PCI_SUBCLASS_RTC 0x03\r
#define PCI_IF_GENERIC_RTC 0x00\r
-#define PCI_IF_ISA_RTC 0x00\r
+#define PCI_IF_ISA_RTC 0x01\r
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
\r
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
#define PCI_SUBCLASS_GAMEPORT 0x04\r
#define PCI_IF_GAMEPORT 0x00\r
-#define PCI_IF_GAMEPORT1 0x01\r
+#define PCI_IF_GAMEPORT1 0x10\r
#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
\r
#define PCI_CLASS_DOCKING_STATION 0x0A\r
+#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r
+#define PCI_SUBCLASS_DOCKING_OTHER 0x80\r
\r
#define PCI_CLASS_PROCESSOR 0x0B\r
#define PCI_SUBCLASS_PROC_386 0x00\r
#define PCI_CLASS_WIRELESS 0x0D\r
#define PCI_SUBCLASS_IRDA 0x00\r
#define PCI_SUBCLASS_IR 0x01\r
-#define PCI_SUBCLASS_RF 0x02\r
+#define PCI_SUBCLASS_RF 0x10\r
#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
\r
#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
\r
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
\r
///\r
/// Capabilities List Header\r
} EFI_PCI_CAPABILITY_HDR;\r
\r
///\r
-/// Power Management Register Block Definition \r
+/// PMC - Power Management Capabilities\r
+/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 Version : 3;\r
+ UINT16 PmeClock : 1;\r
+ UINT16 Reserved : 1;\r
+ UINT16 DeviceSpecificInitialization : 1;\r
+ UINT16 AuxCurrent : 3;\r
+ UINT16 D1Support : 1;\r
+ UINT16 D2Support : 1;\r
+ UINT16 PmeSupport : 5;\r
+ } Bits;\r
+ UINT16 Data;\r
+} EFI_PCI_PMC;\r
+\r
+#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
+\r
+///\r
+/// PMCSR - Power Management Control/Status\r
+/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 PowerState : 2;\r
+ UINT16 ReservedForPciExpress : 1;\r
+ UINT16 NoSoftReset : 1;\r
+ UINT16 Reserved : 4;\r
+ UINT16 PmeEnable : 1;\r
+ UINT16 DataSelect : 4;\r
+ UINT16 DataScale : 2;\r
+ UINT16 PmeStatus : 1;\r
+ } Bits;\r
+ UINT16 Data;\r
+} EFI_PCI_PMCSR;\r
+\r
+#define PCI_POWER_STATE_D0 0\r
+#define PCI_POWER_STATE_D1 1\r
+#define PCI_POWER_STATE_D2 2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 6;\r
+ UINT8 B2B3 : 1;\r
+ UINT8 BusPowerClockControl : 1;\r
+ } Bits;\r
+ UINT8 Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 PMC;\r
- UINT16 PMCSR;\r
- UINT8 BridgeExtention;\r
+ EFI_PCI_PMC PMC;\r
+ EFI_PCI_PMCSR PMCSR;\r
+ EFI_PCI_PMCSR_BSE BridgeExtention;\r
UINT8 Data;\r
} EFI_PCI_CAPABILITY_PMI;\r
\r
///\r
} EFI_PCI_CAPABILITY_HOTPLUG;\r
\r
-#define DEVICE_ID_NOCARE 0xFFFF\r
-\r
-#define PCI_ACPI_UNUSED 0\r
-#define PCI_BAR_NOCHANGE 0\r
-#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
-#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
-\r
#define PCI_BAR_IDX0 0x00\r
#define PCI_BAR_IDX1 0x01\r
#define PCI_BAR_IDX2 0x02\r
#define PCI_BAR_IDX3 0x03\r
#define PCI_BAR_IDX4 0x04\r
#define PCI_BAR_IDX5 0x05\r
-#define PCI_BAR_ALL 0xFF\r
\r
///\r
/// EFI PCI Option ROM definitions\r
projects / mirror_edk2.git / blobdiff