Support for PCI 2.2 standard.\r
\r
This file includes the definitions in the following specifications,\r
- PCI Local Bus Specification, 2.0\r
- PCI-to-PCI Bridge Architecture Specification,\r
+ PCI Local Bus Specification, 2.2\r
+ PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
PC Card Standard, 8.0\r
+ PCI Power Management Interface Specifiction, Revision 1.2\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
+ This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
#ifndef _PCI22_H_\r
#define _PCI22_H_\r
\r
-#define PCI_MAX_SEGMENT 0\r
#define PCI_MAX_BUS 255\r
#define PCI_MAX_DEVICE 31\r
#define PCI_MAX_FUNC 7\r
\r
+#pragma pack(1)\r
\r
+///\r
+/// Common header region in PCI Configuration Space\r
+/// Section 6.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
UINT16 VendorId;\r
UINT16 DeviceId;\r
UINT8 BIST;\r
} PCI_DEVICE_INDEPENDENT_REGION;\r
\r
+///\r
+/// PCI Device header region in PCI Configuration Space\r
+/// Section 6.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
UINT32 Bar[6];\r
UINT32 CISPtr;\r
UINT8 MaxLat;\r
} PCI_DEVICE_HEADER_TYPE_REGION;\r
\r
+///\r
+/// PCI Device Configuration Space\r
+/// Section 6.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
PCI_DEVICE_HEADER_TYPE_REGION Device;\r
} PCI_TYPE00;\r
\r
///\r
-/// defined in PCI-to-PCI Bridge Architecture Specification\r
+/// PCI-PCI Bridge header region in PCI Configuration Space\r
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
///\r
typedef struct {\r
UINT32 Bar[2];\r
UINT16 BridgeControl;\r
} PCI_BRIDGE_CONTROL_REGISTER;\r
\r
+///\r
+/// PCI-to-PCI Bridge Configuration Space\r
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
+///\r
typedef struct {\r
PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
} PCI_TYPE_GENERIC;\r
\r
/// \r
-/// CardBus Conroller Configuration Space, defined in PC Card Standard. 8.0\r
+/// CardBus Conroller Configuration Space, \r
+/// Section 4.5.1, PC Card Standard. 8.0\r
///\r
typedef struct {\r
UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base\r
#define PCI_CLASS_DISPLAY_XGA 0x01\r
#define PCI_CLASS_DISPLAY_3D 0x02\r
#define PCI_CLASS_DISPLAY_OTHER 0x80 \r
-#define PCI_CLASS_DISPLAY_GFX 0x80\r
\r
#define PCI_CLASS_MEDIA 0x04\r
#define PCI_CLASS_MEDIA_VIDEO 0x00\r
#define PCI_IF_16550_MODEM 0x02\r
#define PCI_IF_16650_MODEM 0x03\r
#define PCI_IF_16750_MODEM 0x04\r
-#define PCI_SUBCLASS_SCC_OTHER 0x80\r
+#define PCI_SUBCLASS_SCC_OTHER 0x80\r
\r
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
#define PCI_SUBCLASS_PIC 0x00\r
#define PCI_IF_EISA_TIMER 0x02\r
#define PCI_SUBCLASS_RTC 0x03\r
#define PCI_IF_GENERIC_RTC 0x00\r
-#define PCI_IF_ISA_RTC 0x00\r
+#define PCI_IF_ISA_RTC 0x01\r
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
\r
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
#define PCI_SUBCLASS_GAMEPORT 0x04\r
#define PCI_IF_GAMEPORT 0x00\r
-#define PCI_IF_GAMEPORT1 0x01\r
+#define PCI_IF_GAMEPORT1 0x10\r
#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
\r
#define PCI_CLASS_DOCKING_STATION 0x0A\r
+#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r
+#define PCI_SUBCLASS_DOCKING_OTHER 0x80\r
\r
#define PCI_CLASS_PROCESSOR 0x0B\r
#define PCI_SUBCLASS_PROC_386 0x00\r
#define PCI_CLASS_WIRELESS 0x0D\r
#define PCI_SUBCLASS_IRDA 0x00\r
#define PCI_SUBCLASS_IR 0x01\r
-#define PCI_SUBCLASS_RF 0x02\r
+#define PCI_SUBCLASS_RF 0x10\r
#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
\r
#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
#define PCI_SUBCLASS_DPIO 0x00\r
#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
\r
+/** \r
+ Macro that checks whether the Base Class code of device matched.\r
+\r
+ @param _p Specified device.\r
+ @param c Base Class code needs matching.\r
+\r
+ @retval TRUE Base Class code matches the specified device.\r
+ @retval FALSE Base Class code doesn't match the specified device. \r
+\r
+**/\r
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
+/** \r
+ Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
+\r
+ @param _p Specified device.\r
+ @param c Base Class code needs matching.\r
+ @param s Sub-Class code needs matching.\r
+\r
+ @retval TRUE Base Class code and Sub-Class code match the specified device.\r
+ @retval FALSE Base Class code and Sub-Class code don't match the specified device. \r
+\r
+**/\r
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
+/** \r
+ Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
+\r
+ @param _p Specified device.\r
+ @param c Base Class code needs matching.\r
+ @param s Sub-Class code needs matching.\r
+ @param p Interface code needs matching.\r
+\r
+ @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
+ @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. \r
+\r
+**/\r
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
\r
+/** \r
+ Macro that checks whether device is a display controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a display controller.\r
+ @retval FALSE Device is not a display controller.\r
+\r
+**/\r
#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
-#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)\r
-#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)\r
-#define IS_PCI_GFX(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)\r
+/** \r
+ Macro that checks whether device is a VGA-compatible controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a VGA-compatible controller.\r
+ @retval FALSE Device is not a VGA-compatible controller.\r
+\r
+**/\r
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
+/** \r
+ Macro that checks whether device is an 8514-compatible controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an 8514-compatible controller.\r
+ @retval FALSE Device is not an 8514-compatible controller.\r
+\r
+**/\r
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
+/** \r
+ Macro that checks whether device is built before the Class Code field was defined.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an old device.\r
+ @retval FALSE Device is not an old device.\r
+\r
+**/\r
#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
+/** \r
+ Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an old VGA-compatible device.\r
+ @retval FALSE Device is not an old VGA-compatible device.\r
+\r
+**/\r
#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
+/** \r
+ Macro that checks whether device is an IDE controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an IDE controller.\r
+ @retval FALSE Device is not an IDE controller.\r
+\r
+**/\r
#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
-#define IS_PCI_SCSI(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)\r
-#define IS_PCI_RAID(_p) IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)\r
-#define IS_PCI_LPC(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)\r
-#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)\r
-#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)\r
+/** \r
+ Macro that checks whether device is a SCSI bus controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a SCSI bus controller.\r
+ @retval FALSE Device is not a SCSI bus controller.\r
+\r
+**/\r
+#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
+/** \r
+ Macro that checks whether device is a RAID controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a RAID controller.\r
+ @retval FALSE Device is not a RAID controller.\r
+\r
+**/\r
+#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
+/** \r
+ Macro that checks whether device is an ISA bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is an ISA bridge.\r
+ @retval FALSE Device is not an ISA bridge.\r
+\r
+**/\r
+#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
+/** \r
+ Macro that checks whether device is a PCI-to-PCI bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a PCI-to-PCI bridge.\r
+ @retval FALSE Device is not a PCI-to-PCI bridge.\r
+\r
+**/\r
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
+/** \r
+ Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r
+ @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
+\r
+**/\r
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
+/** \r
+ Macro that checks whether device is a 16550-compatible serial controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a 16550-compatible serial controller.\r
+ @retval FALSE Device is not a 16550-compatible serial controller.\r
+\r
+**/\r
#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+/** \r
+ Macro that checks whether device is a Universal Serial Bus controller.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a Universal Serial Bus controller.\r
+ @retval FALSE Device is not a Universal Serial Bus controller.\r
+\r
+**/\r
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
\r
//\r
// Mask of Header type\r
//\r
#define HEADER_LAYOUT_CODE 0x7f\r
+/** \r
+ Macro that checks whether device is a PCI-PCI bridge.\r
+\r
+ @param _p Specified device.\r
\r
+ @retval TRUE Device is a PCI-PCI bridge.\r
+ @retval FALSE Device is not a PCI-PCI bridge.\r
+\r
+**/\r
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
+/** \r
+ Macro that checks whether device is a CardBus bridge.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a CardBus bridge.\r
+ @retval FALSE Device is not a CardBus bridge.\r
+\r
+**/\r
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
+/** \r
+ Macro that checks whether device is a multiple functions device.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a multiple functions device.\r
+ @retval FALSE Device is not a multiple functions device.\r
+\r
+**/\r
#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
\r
///\r
#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
\r
///\r
#define PCI_INT_LINE_UNKNOWN 0xFF \r
\r
+///\r
+/// PCI Access Data Format\r
+///\r
typedef union {\r
struct {\r
UINT32 Reg : 8;\r
UINT32 Uint32;\r
} PCI_CONFIG_ACCESS_CF8;\r
\r
+#pragma pack()\r
+\r
#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
///\r
#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
\r
+#pragma pack(1)\r
//\r
// PCI Capability List IDs and records\r
//\r
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
\r
+///\r
+/// Capabilities List Header\r
+/// Section 6.7, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
UINT8 CapabilityID;\r
UINT8 NextItemPtr;\r
} EFI_PCI_CAPABILITY_HDR;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_PMI, defined in PCI Power Management Interface Specifiction\r
+/// PMC - Power Management Capabilities\r
+/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 Version : 3;\r
+ UINT16 PmeClock : 1;\r
+ UINT16 Reserved : 1;\r
+ UINT16 DeviceSpecificInitialization : 1;\r
+ UINT16 AuxCurrent : 3;\r
+ UINT16 D1Support : 1;\r
+ UINT16 D2Support : 1;\r
+ UINT16 PmeSupport : 5;\r
+ } Bits;\r
+ UINT16 Data;\r
+} EFI_PCI_PMC;\r
+\r
+#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
+\r
+///\r
+/// PMCSR - Power Management Control/Status\r
+/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT16 PowerState : 2;\r
+ UINT16 ReservedForPciExpress : 1;\r
+ UINT16 NoSoftReset : 1;\r
+ UINT16 Reserved : 4;\r
+ UINT16 PmeEnable : 1;\r
+ UINT16 DataSelect : 4;\r
+ UINT16 DataScale : 2;\r
+ UINT16 PmeStatus : 1;\r
+ } Bits;\r
+ UINT16 Data;\r
+} EFI_PCI_PMCSR;\r
+\r
+#define PCI_POWER_STATE_D0 0\r
+#define PCI_POWER_STATE_D1 1\r
+#define PCI_POWER_STATE_D2 2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 6;\r
+ UINT8 B2B3 : 1;\r
+ UINT8 BusPowerClockControl : 1;\r
+ } Bits;\r
+ UINT8 Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 PMC;\r
- UINT16 PMCSR;\r
- UINT8 BridgeExtention;\r
+ EFI_PCI_PMC PMC;\r
+ EFI_PCI_PMCSR PMCSR;\r
+ EFI_PCI_PMCSR_BSE BridgeExtention;\r
UINT8 Data;\r
} EFI_PCI_CAPABILITY_PMI;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_AGP, defined in Accelerated Graphics Port Interface Specification\r
+/// A.G.P Capability\r
+/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
} EFI_PCI_CAPABILITY_AGP;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_VPD, in PCI2.2 Spec.\r
+/// VPD Capability Structure\r
+/// Appendix I, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
} EFI_PCI_CAPABILITY_VPD;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_SLOTID, defined in PCI-to-PCI Bridge Architeture Specification\r
+/// Slot Numbering Capabilities Register\r
+/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
} EFI_PCI_CAPABILITY_SLOTID;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_MSI, defined in PCI2.2\r
+/// Message Capability Structure for 32-bit Message Address\r
+/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
UINT16 MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI32;\r
\r
+///\r
+/// Message Capability Structure for 64-bit Message Address\r
+/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
UINT16 MsgCtrlReg;\r
} EFI_PCI_CAPABILITY_MSI64;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, defined in CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r
+/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
///\r
typedef struct {\r
EFI_PCI_CAPABILITY_HDR Hdr;\r
///\r
} EFI_PCI_CAPABILITY_HOTPLUG;\r
\r
-#define DEVICE_ID_NOCARE 0xFFFF\r
-\r
-#define PCI_ACPI_UNUSED 0\r
-#define PCI_BAR_NOCHANGE 0\r
-#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL\r
-#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL\r
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL\r
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL\r
-\r
#define PCI_BAR_IDX0 0x00\r
#define PCI_BAR_IDX1 0x01\r
#define PCI_BAR_IDX2 0x02\r
#define PCI_BAR_IDX3 0x03\r
#define PCI_BAR_IDX4 0x04\r
#define PCI_BAR_IDX5 0x05\r
-#define PCI_BAR_ALL 0xFF\r
\r
///\r
/// EFI PCI Option ROM definitions\r
#define EFI_ROOT_BRIDGE_LIST 'eprb' \r
#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
\r
-typedef struct {\r
- UINT8 Register;\r
- UINT8 Function;\r
- UINT8 Device;\r
- UINT8 Bus;\r
- UINT8 Reserved[4];\r
-} DEFIO_PCI_ADDR;\r
-\r
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///<defined in UEFI spec.\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
\r
+///\r
+/// Standard PCI Expansion ROM Header\r
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
+///\r
typedef struct {\r
UINT16 Signature; ///< 0xaa55\r
UINT8 Reserved[0x16];\r
UINT16 PcirOffset;\r
} PCI_EXPANSION_ROM_HEADER;\r
\r
+///\r
+/// Legacy ROM Header Extensions\r
+/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
UINT16 Signature; ///< 0xaa55\r
UINT8 Size512;\r
UINT16 PcirOffset;\r
} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
\r
+///\r
+/// PCI Data Structure Format\r
+/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
+///\r
typedef struct {\r
UINT32 Signature; ///< "PCIR"\r
UINT16 VendorId;\r
} PCI_DATA_STRUCTURE;\r
\r
///\r
-/// defined in EFI/UEFI Spec\r
+/// EFI PCI Expansion ROM Header\r
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
///\r
typedef struct {\r
UINT16 Signature; ///< 0xaa55\r
EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
} EFI_PCI_ROM_HEADER;\r
\r
+#pragma pack()\r
+\r
#endif\r
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