PC Card Standard, 8.0\r
PCI Power Management Interface Specifiction, Revision 1.2\r
\r
- Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
PCI_TYPE01 Bridge;\r
} PCI_TYPE_GENERIC;\r
\r
-/// \r
-/// CardBus Conroller Configuration Space, \r
+///\r
+/// CardBus Conroller Configuration Space,\r
/// Section 4.5.1, PC Card Standard. 8.0\r
///\r
typedef struct {\r
#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
\r
#define PCI_CLASS_NETWORK 0x02\r
-#define PCI_CLASS_NETWORK_ETHERNET 0x00 \r
+#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
#define PCI_CLASS_NETWORK_FDDI 0x02\r
#define PCI_CLASS_NETWORK_ATM 0x03\r
#define PCI_IF_VGA_8514 0x01\r
#define PCI_CLASS_DISPLAY_XGA 0x01\r
#define PCI_CLASS_DISPLAY_3D 0x02\r
-#define PCI_CLASS_DISPLAY_OTHER 0x80 \r
+#define PCI_CLASS_DISPLAY_OTHER 0x80\r
\r
#define PCI_CLASS_MEDIA 0x04\r
#define PCI_CLASS_MEDIA_VIDEO 0x00\r
#define PCI_CLASS_BRIDGE_OTHER 0x80\r
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
\r
-#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers \r
+#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers\r
#define PCI_SUBCLASS_SERIAL 0x00\r
#define PCI_IF_GENERIC_XT 0x00\r
#define PCI_IF_16450 0x01\r
#define PCI_IF_8259_PIC 0x00\r
#define PCI_IF_ISA_PIC 0x01\r
#define PCI_IF_EISA_PIC 0x02\r
-#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory. \r
-#define PCI_IF_APIC_CONTROLLER2 0x20 \r
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.\r
+#define PCI_IF_APIC_CONTROLLER2 0x20\r
#define PCI_SUBCLASS_DMA 0x01\r
#define PCI_IF_8237_DMA 0x00\r
#define PCI_IF_ISA_DMA 0x01\r
\r
#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
#define PCI_SUBCLASS_NET_COMPUT 0x00\r
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10 \r
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10\r
#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
\r
#define PCI_CLASS_DPIO 0x11\r
#define PCI_SUBCLASS_DPIO 0x00\r
#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
\r
-/** \r
+/**\r
Macro that checks whether the Base Class code of device matched.\r
\r
@param _p Specified device.\r
@param c Base Class code needs matching.\r
\r
@retval TRUE Base Class code matches the specified device.\r
- @retval FALSE Base Class code doesn't match the specified device. \r
+ @retval FALSE Base Class code doesn't match the specified device.\r
\r
**/\r
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
-/** \r
+/**\r
Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
\r
@param _p Specified device.\r
@param s Sub-Class code needs matching.\r
\r
@retval TRUE Base Class code and Sub-Class code match the specified device.\r
- @retval FALSE Base Class code and Sub-Class code don't match the specified device. \r
+ @retval FALSE Base Class code and Sub-Class code don't match the specified device.\r
\r
**/\r
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
-/** \r
+/**\r
Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
\r
@param _p Specified device.\r
@param p Interface code needs matching.\r
\r
@retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r
- @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. \r
+ @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.\r
\r
**/\r
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
\r
-/** \r
+/**\r
Macro that checks whether device is a display controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
-/** \r
+/**\r
Macro that checks whether device is a VGA-compatible controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
-/** \r
+/**\r
Macro that checks whether device is an 8514-compatible controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
-/** \r
+/**\r
Macro that checks whether device is built before the Class Code field was defined.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
-/** \r
+/**\r
Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
-/** \r
+/**\r
Macro that checks whether device is an IDE controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
-/** \r
+/**\r
Macro that checks whether device is a SCSI bus controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
-/** \r
+/**\r
Macro that checks whether device is a RAID controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
-/** \r
+/**\r
Macro that checks whether device is an ISA bridge.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
-/** \r
+/**\r
Macro that checks whether device is a PCI-to-PCI bridge.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
-/** \r
+/**\r
Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
-/** \r
+/**\r
Macro that checks whether device is a 16550-compatible serial controller.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
-/** \r
+/**\r
Macro that checks whether device is a Universal Serial Bus controller.\r
\r
@param _p Specified device.\r
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
\r
//\r
-// the definition of Header Type \r
+// the definition of Header Type\r
//\r
#define HEADER_TYPE_DEVICE 0x00\r
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
// Mask of Header type\r
//\r
#define HEADER_LAYOUT_CODE 0x7f\r
-/** \r
+/**\r
Macro that checks whether device is a PCI-PCI bridge.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
-/** \r
+/**\r
Macro that checks whether device is a CardBus bridge.\r
\r
@param _p Specified device.\r
\r
**/\r
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
-/** \r
+/**\r
Macro that checks whether device is a multiple functions device.\r
\r
@param _p Specified device.\r
//\r
// defined in PCI-to-PCI Bridge Architecture Specification\r
//\r
-#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 \r
-#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 \r
-#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a \r
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\r
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r
#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E \r
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E \r
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r
\r
///\r
/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
///\r
-#define PCI_INT_LINE_UNKNOWN 0xFF \r
+#define PCI_INT_LINE_UNKNOWN 0xFF\r
\r
///\r
/// PCI Access Data Format\r
} EFI_PCI_CAPABILITY_MSI64;\r
\r
///\r
-/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, \r
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,\r
/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
///\r
typedef struct {\r
\r
///\r
/// EFI PCI Option ROM definitions\r
-/// \r
-#define EFI_ROOT_BRIDGE_LIST 'eprb' \r
+///\r
+#define EFI_ROOT_BRIDGE_LIST 'eprb'\r
#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
\r
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
projects / mirror_edk2.git / blobdiff