\r
typedef union {\r
struct {\r
- UINT8 BytesUsed : 4; ///< Bits 3:0\r
- UINT8 BytesTotal : 3; ///< Bits 6:4\r
- UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_DEVICE_DESCRIPTION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Minor : 4; ///< Bits 3:0\r
- UINT8 Major : 4; ///< Bits 7:4\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_REVISION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Type : 8; ///< Bits 7:0\r
+ UINT8 Type : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_DRAM_DEVICE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ModuleType : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Density : 4; ///< Bits 3:0\r
- UINT8 BankAddress : 3; ///< Bits 6:4\r
- UINT8 Reserved : 1; ///< Bits 7:7\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 3; ///< Bits 6:4\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_DENSITY_BANKS_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ColumnAddress : 3; ///< Bits 2:0\r
- UINT8 RowAddress : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_ADDRESSING_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r
- UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r
- UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r
- UINT8 Reserved : 5; ///< Bits 7:3\r
+ UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r
+ UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r
+ UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r
+ UINT8 Reserved : 5; ///< Bits 7:3\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
- UINT8 RankCount : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_ORGANIZATION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
- UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Divisor : 4; ///< Bits 3:0\r
- UINT8 Dividend : 4; ///< Bits 7:4\r
+ UINT8 Divisor : 4; ///< Bits 3:0\r
+ UINT8 Dividend : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_FINE_TIMEBASE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Dividend : 8; ///< Bits 7:0\r
+ UINT8 Dividend : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Divisor : 8; ///< Bits 7:0\r
+ UINT8 Divisor : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;\r
\r
typedef struct {\r
- SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r
- SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r
+ SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r
+ SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r
} SPD3_MEDIUM_TIMEBASE;\r
\r
typedef union {\r
struct {\r
- UINT8 tCKmin : 8; ///< Bits 7:0\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TCK_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 Cl4 : 1; ///< Bits 0:0\r
- UINT16 Cl5 : 1; ///< Bits 1:1\r
- UINT16 Cl6 : 1; ///< Bits 2:2\r
- UINT16 Cl7 : 1; ///< Bits 3:3\r
- UINT16 Cl8 : 1; ///< Bits 4:4\r
- UINT16 Cl9 : 1; ///< Bits 5:5\r
- UINT16 Cl10 : 1; ///< Bits 6:6\r
- UINT16 Cl11 : 1; ///< Bits 7:7\r
- UINT16 Cl12 : 1; ///< Bits 8:8\r
- UINT16 Cl13 : 1; ///< Bits 9:9\r
- UINT16 Cl14 : 1; ///< Bits 10:10\r
- UINT16 Cl15 : 1; ///< Bits 11:11\r
- UINT16 Cl16 : 1; ///< Bits 12:12\r
- UINT16 Cl17 : 1; ///< Bits 13:13\r
- UINT16 Cl18 : 1; ///< Bits 14:14\r
- UINT16 Reserved : 1; ///< Bits 15:15\r
- } Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Cl4 : 1; ///< Bits 0:0\r
+ UINT16 Cl5 : 1; ///< Bits 1:1\r
+ UINT16 Cl6 : 1; ///< Bits 2:2\r
+ UINT16 Cl7 : 1; ///< Bits 3:3\r
+ UINT16 Cl8 : 1; ///< Bits 4:4\r
+ UINT16 Cl9 : 1; ///< Bits 5:5\r
+ UINT16 Cl10 : 1; ///< Bits 6:6\r
+ UINT16 Cl11 : 1; ///< Bits 7:7\r
+ UINT16 Cl12 : 1; ///< Bits 8:8\r
+ UINT16 Cl13 : 1; ///< Bits 9:9\r
+ UINT16 Cl14 : 1; ///< Bits 10:10\r
+ UINT16 Cl15 : 1; ///< Bits 11:11\r
+ UINT16 Cl16 : 1; ///< Bits 12:12\r
+ UINT16 Cl17 : 1; ///< Bits 13:13\r
+ UINT16 Cl18 : 1; ///< Bits 14:14\r
+ UINT16 Reserved : 1; ///< Bits 15:15\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tAAmin : 8; ///< Bits 7:0\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TAA_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWRmin : 8; ///< Bits 7:0\r
+ UINT8 tWRmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TWR_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRCD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRRDmin : 8; ///< Bits 7:0\r
+ UINT8 tRRDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRRD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRPmin : 8; ///< Bits 7:0\r
+ UINT8 tRPmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRP_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRASminUpper : 4; ///< Bits 3:0\r
- UINT8 tRCminUpper : 4; ///< Bits 7:4\r
+ UINT8 tRASminUpper : 4; ///< Bits 3:0\r
+ UINT8 tRCminUpper : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRAS_TRC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRASmin : 8; ///< Bits 7:0\r
+ UINT8 tRASmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRAS_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCmin : 8; ///< Bits 7:0\r
+ UINT8 tRCmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 tRFCmin : 16; ///< Bits 15:0\r
+ UINT16 tRFCmin : 16; ///< Bits 15:0\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD3_TRFC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWTRmin : 8; ///< Bits 7:0\r
+ UINT8 tWTRmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TWTR_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRTPmin : 8; ///< Bits 7:0\r
+ UINT8 tRTPmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRTP_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tFAWmin : 8; ///< Bits 7:0\r
+ UINT8 tFAWmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TFAW_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Rzq6 : 1; ///< Bits 0:0\r
- UINT8 Rzq7 : 1; ///< Bits 1:1\r
- UINT8 Reserved : 5; ///< Bits 6:2\r
- UINT8 DllOff : 1; ///< Bits 7:7\r
+ UINT8 Rzq6 : 1; ///< Bits 0:0\r
+ UINT8 Rzq7 : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 5; ///< Bits 6:2\r
+ UINT8 DllOff : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r
- UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r
- UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r
- UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r
- UINT8 Reserved : 3; ///< Bits 6:4\r
- UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r
+ UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r
+ UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r
+ UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r
+ UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r
+ UINT8 Reserved : 3; ///< Bits 6:4\r
+ UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r
- UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_THERMAL_SENSOR_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SignalLoading : 2; ///< Bits 1:0\r
- UINT8 Reserved : 2; ///< Bits 3:2\r
- UINT8 DieCount : 3; ///< Bits 6:4\r
- UINT8 SdramDeviceType : 1; ///< Bits 7:7\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 Reserved : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramDeviceType : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_DEVICE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCKminFine : 8; ///< Bits 7:0\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TCK_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tAAminFine : 8; ///< Bits 7:0\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TAA_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TRCD_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRPminFine : 8; ///< Bits 7:0\r
+ INT8 tRPminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TRP_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCminFine : 8; ///< Bits 7:0\r
+ INT8 tRCminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TRC_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
- UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
- UINT8 VendorSpecific : 2; ///< Bits 7:6\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 VendorSpecific : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 MappingRank1 : 1; ///< Bits 0:0\r
- UINT8 Reserved : 7; ///< Bits 7:1\r
+ UINT8 MappingRank1 : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_ADDRESS_MAPPING;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterCount : 2; ///< Bits 1:0\r
- UINT8 DramRowCount : 2; ///< Bits 3:2\r
- UINT8 RegisterType : 4; ///< Bits 7:4\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_MODULE_ATTRIBUTES;\r
\r
typedef union {\r
struct {\r
- UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
- UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
\r
typedef union {\r
struct {\r
- UINT16 ContinuationCount : 7; ///< Bits 6:0\r
- UINT16 ContinuationParity : 1; ///< Bits 7:7\r
- UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD3_MANUFACTURER_ID_CODE;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_REVISION_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 Bit0 : 1; ///< Bits 0:0\r
- UINT8 Bit1 : 1; ///< Bits 1:1\r
- UINT8 Bit2 : 1; ///< Bits 2:2\r
- UINT8 Reserved : 5; ///< Bits 7:3\r
+ UINT8 Bit0 : 1; ///< Bits 0:0\r
+ UINT8 Bit1 : 1; ///< Bits 1:1\r
+ UINT8 Bit2 : 1; ///< Bits 2:2\r
+ UINT8 Reserved : 5; ///< Bits 7:3\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 4; ///< Bits 0:3\r
- UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r
- UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r
+ UINT8 Reserved : 4; ///< Bits 0:3\r
+ UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r
+ UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r
- UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r
- UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
- UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
+ UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r
+ UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved0 : 4; ///< Bits 0:3\r
- UINT8 Reserved1 : 4; ///< Bits 7:4\r
+ UINT8 Reserved0 : 4; ///< Bits 0:3\r
+ UINT8 Reserved1 : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterCount : 2; ///< Bits 1:0\r
- UINT8 DramRowCount : 2; ///< Bits 3:2\r
- UINT8 RegisterType : 4; ///< Bits 7:4\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_ATTRIBUTES;\r
\r
typedef union {\r
struct {\r
- UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r
- UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r
- UINT8 Reserved0 : 1; ///< Bits 2:2\r
- UINT8 Reserved1 : 1; ///< Bits 3:3\r
- UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r
- UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r
+ UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r
+ UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r
+ UINT8 Reserved0 : 1; ///< Bits 2:2\r
+ UINT8 Reserved1 : 1; ///< Bits 3:3\r
+ UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r
+ UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r
- UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r
- UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
- UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
+ UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r
+ UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 YExtendedDelay : 2; ///< Bits 1:0\r
- UINT8 QxCS_n : 2; ///< Bits 3:2\r
- UINT8 QxOdt : 2; ///< Bits 5:4\r
- UINT8 QxCke : 2; ///< Bits 7:6\r
+ UINT8 YExtendedDelay : 2; ///< Bits 1:0\r
+ UINT8 QxCS_n : 2; ///< Bits 3:2\r
+ UINT8 QxOdt : 2; ///< Bits 5:4\r
+ UINT8 QxCke : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_EXTENDED_DELAY;\r
\r
typedef union {\r
struct {\r
- UINT8 DelayY : 3; ///< Bits 2:0\r
- UINT8 Reserved : 1; ///< Bits 3:3\r
- UINT8 QxCS_n : 4; ///< Bits 7:4\r
+ UINT8 DelayY : 3; ///< Bits 2:0\r
+ UINT8 Reserved : 1; ///< Bits 3:3\r
+ UINT8 QxCS_n : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;\r
\r
typedef union {\r
struct {\r
- UINT8 QxCS_n : 4; ///< Bits 3:0\r
- UINT8 QxOdt : 4; ///< Bits 7:4\r
+ UINT8 QxCS_n : 4; ///< Bits 3:0\r
+ UINT8 QxOdt : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;\r
\r
typedef union {\r
struct {\r
- UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r
- UINT8 RC8Reserved : 1; ///< Bits 3:3\r
- UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r
- UINT8 RC9Reserved : 1; ///< Bits 7:7\r
+ UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r
+ UINT8 RC8Reserved : 1; ///< Bits 3:3\r
+ UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r
+ UINT8 RC9Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r
- UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r
- UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r
- UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r
- UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r
- UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r
- UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r
- UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r
+ UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r
+ UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r
+ UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r
+ UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r
+ UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r
+ UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r
+ UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r
+ UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT8 Driver_Impedance : 2; ///< Bits 1:0\r
- UINT8 Rtt_Nom : 3; ///< Bits 4:2\r
- UINT8 Reserved : 1; ///< Bits 5:5\r
- UINT8 Rtt_WR : 2; ///< Bits 7:6\r
+ UINT8 Driver_Impedance : 2; ///< Bits 1:0\r
+ UINT8 Rtt_Nom : 3; ///< Bits 4:2\r
+ UINT8 Reserved : 1; ///< Bits 5:5\r
+ UINT8 Rtt_WR : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MR_1_2;\r
\r
typedef union {\r
struct {\r
- UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r
- UINT8 Reserved : 1; ///< Bits 7:7\r
+ UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_DELAY_TIME;\r
\r
typedef struct {\r
- UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
- UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
} SPD3_MANUFACTURING_DATE;\r
\r
typedef union {\r
- UINT32 Data;\r
- UINT16 SerialNumber16[2];\r
- UINT8 SerialNumber8[4];\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
} SPD3_MANUFACTURER_SERIAL_NUMBER;\r
\r
typedef struct {\r
- UINT8 Location; ///< Module Manufacturing Location\r
+ UINT8 Location; ///< Module Manufacturing Location\r
} SPD3_MANUFACTURING_LOCATION;\r
\r
typedef struct {\r
- SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
- SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
- SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
- SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+ SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
} SPD3_UNIQUE_MODULE_ID;\r
\r
typedef union {\r
- UINT16 Crc[1];\r
- UINT8 Data8[2];\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
} SPD3_CYCLIC_REDUNDANCY_CODE;\r
\r
typedef struct {\r
- SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
- SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
- SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
- SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
- SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
- SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
- SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r
- SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r
- SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r
- SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r
- SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r
- SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r
- UINT8 Reserved0; ///< 13 Reserved\r
- SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r
- SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r
- SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r
- SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r
- SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r
- SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r
- SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
- SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
- SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r
- SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r
- SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r
- SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r
- SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r
- SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r
- SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r
- SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r
- SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r
- SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
- SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
- SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r
- SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
- UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r
- SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r
- UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r
+ SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r
+ SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r
+ SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r
+ SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r
+ SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r
+ SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r
+ UINT8 Reserved0; ///< 13 Reserved\r
+ SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r
+ SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r
+ SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r
+ SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r
+ SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r
+ SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
+ SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
+ SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r
+ SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r
+ SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r
+ SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r
+ SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r
+ SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r
+ SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r
+ SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r
+ SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r
+ SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
+ UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r
+ SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r
+ UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r
} SPD3_BASE_SECTION;\r
\r
typedef struct {\r
- SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r
- UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r
+ UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r
} SPD3_MODULE_UNBUFFERED;\r
\r
typedef struct {\r
- SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r
- SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r
- SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r
- SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r
- SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r
- SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r
- UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r
+ SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r
+ SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r
+ SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r
+ SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r
+ SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r
+ SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r
+ UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r
} SPD3_MODULE_REGISTERED;\r
\r
typedef struct {\r
- SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r
} SPD3_MODULE_CLOCKED;\r
\r
typedef struct {\r
- SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r
- UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r
- SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r
- SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r
- SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r
- SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r
- SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r
- SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r
+ UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r
+ SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r
+ SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r
+ SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r
+ SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r
- UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r
- UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r
+ UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r
+ UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r
} SPD3_MODULE_LOADREDUCED;\r
\r
typedef union {\r
- SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
- SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
- SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r
- SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
+ SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
+ SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
+ SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r
+ SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
} SPD3_MODULE_SPECIFIC;\r
\r
typedef struct {\r
- UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r
+ UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r
} SPD3_MODULE_PART_NUMBER;\r
\r
typedef struct {\r
- UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r
+ UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r
} SPD3_MODULE_REVISION_CODE;\r
\r
typedef struct {\r
- UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data\r
+ UINT8 ManufacturerSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data\r
} SPD3_MANUFACTURER_SPECIFIC;\r
\r
///\r
/// DDR3 Serial Presence Detect structure\r
///\r
typedef struct {\r
- SPD3_BASE_SECTION General; ///< 0-59 General Section\r
- SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r
- SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r
- SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
- SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r
- SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r
- SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r
- SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r
- UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r
+ SPD3_BASE_SECTION General; ///< 0-59 General Section\r
+ SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r
+ SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r
+ SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+ SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r
+ SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r
+ SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r
+ SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r
+ UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r
} SPD_DDR3;\r
\r
#pragma pack (pop)\r
projects / mirror_edk2.git / blobdiff