--- /dev/null
+/** @file\r
+ Platform TPM Profile Specification definition for TPM2.0.\r
+ It covers both FIFO and CRB interface.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _TPM_PTP_H_\r
+#define _TPM_PTP_H_\r
+\r
+//\r
+// PTP FIFO definition\r
+//\r
+\r
+//\r
+// Set structure alignment to 1-byte\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// Register set map as specified in PTP specification Chapter 5\r
+//\r
+typedef struct {\r
+ ///\r
+ /// Used to gain ownership for this particular port.\r
+ ///\r
+ UINT8 Access; // 0\r
+ UINT8 Reserved1[7]; // 1\r
+ ///\r
+ /// Controls interrupts.\r
+ ///\r
+ UINT32 IntEnable; // 8\r
+ ///\r
+ /// SIRQ vector to be used by the TPM.\r
+ ///\r
+ UINT8 IntVector; // 0ch\r
+ UINT8 Reserved2[3]; // 0dh\r
+ ///\r
+ /// What caused interrupt.\r
+ ///\r
+ UINT32 IntSts; // 10h\r
+ ///\r
+ /// Shows which interrupts are supported by that particular TPM.\r
+ ///\r
+ UINT32 InterfaceCapability;// 14h\r
+ ///\r
+ /// Status Register. Provides status of the TPM.\r
+ ///\r
+ UINT8 Status; // 18h\r
+ ///\r
+ /// Number of consecutive writes that can be done to the TPM.\r
+ ///\r
+ UINT16 BurstCount; // 19h\r
+ ///\r
+ /// Additional Status Register.\r
+ ///\r
+ UINT8 StatusEx; // 1Bh\r
+ UINT8 Reserved3[8];\r
+ ///\r
+ /// Read or write FIFO, depending on transaction.\r
+ ///\r
+ UINT32 DataFifo; // 24h\r
+ UINT8 Reserved4[8]; // 28h\r
+ ///\r
+ /// Used to identify the Interface types supported by the TPM.\r
+ ///\r
+ UINT32 InterfaceId; // 30h\r
+ UINT8 Reserved5[0x4c]; // 34h\r
+ ///\r
+ /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r
+ ///\r
+ UINT32 XDataFifo; // 80h\r
+ UINT8 Reserved6[0xe7c]; // 84h\r
+ ///\r
+ /// Vendor ID\r
+ ///\r
+ UINT16 Vid; // 0f00h\r
+ ///\r
+ /// Device ID\r
+ ///\r
+ UINT16 Did; // 0f02h\r
+ ///\r
+ /// Revision ID\r
+ ///\r
+ UINT8 Rid; // 0f04h\r
+ UINT8 Reserved[0xfb]; // 0f05h\r
+} PTP_FIFO_REGISTERS;\r
+\r
+//\r
+// Restore original structure alignment\r
+//\r
+#pragma pack ()\r
+\r
+//\r
+// Define pointer types used to access TIS registers on PC\r
+//\r
+typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r
+\r
+//\r
+// Define bits of FIFO Interface Identifier Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 InterfaceType:4;\r
+ UINT32 InterfaceVersion:4;\r
+ UINT32 CapLocality:1;\r
+ UINT32 Reserved1:2;\r
+ UINT32 CapDataXferSizeSupport:2;\r
+ UINT32 CapFIFO:1;\r
+ UINT32 CapCRB:1;\r
+ UINT32 CapIFRes:2;\r
+ UINT32 InterfaceSelector:2;\r
+ UINT32 IntfSelLock:1;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Reserved3:8;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PTP_FIFO_INTERFACE_IDENTIFIER;\r
+\r
+//\r
+// Define bits of FIFO Interface Capability Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 DataAvailIntSupport:1;\r
+ UINT32 StsValidIntSupport:1;\r
+ UINT32 LocalityChangeIntSupport:1;\r
+ UINT32 InterruptLevelHigh:1;\r
+ UINT32 InterruptLevelLow:1;\r
+ UINT32 InterruptEdgeRising:1;\r
+ UINT32 InterruptEdgeFalling:1;\r
+ UINT32 CommandReadyIntSupport:1;\r
+ UINT32 BurstCountStatic:1;\r
+ UINT32 DataTransferSizeSupport:2;\r
+ UINT32 Reserved:17;\r
+ UINT32 InterfaceVersion:3;\r
+ UINT32 Reserved2:1;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PTP_FIFO_INTERFACE_CAPABILITY;\r
+\r
+///\r
+/// InterfaceVersion\r
+///\r
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0\r
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2\r
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3\r
+\r
+\r
+//\r
+// Define bits of ACCESS and STATUS registers\r
+//\r
+\r
+///\r
+/// This bit is a 1 to indicate that the other bits in this register are valid.\r
+///\r
+#define PTP_FIFO_VALID BIT7\r
+///\r
+/// Indicate that this locality is active.\r
+///\r
+#define PTP_FIFO_ACC_ACTIVE BIT5\r
+///\r
+/// Set to 1 to indicate that this locality had the TPM taken away while\r
+/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
+///\r
+#define PTP_FIFO_ACC_SEIZED BIT4\r
+///\r
+/// Set to 1 to indicate that TPM MUST reset the\r
+/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
+/// locality that is writing this bit.\r
+///\r
+#define PTP_FIFO_ACC_SEIZE BIT3\r
+///\r
+/// When this bit is 1, another locality is requesting usage of the TPM.\r
+///\r
+#define PTP_FIFO_ACC_PENDIND BIT2\r
+///\r
+/// Set to 1 to indicate that this locality is requesting to use TPM.\r
+///\r
+#define PTP_FIFO_ACC_RQUUSE BIT1\r
+///\r
+/// A value of 1 indicates that a T/OS has not been established on the platform\r
+///\r
+#define PTP_FIFO_ACC_ESTABLISH BIT0\r
+\r
+///\r
+/// This field indicates that STS_DATA and STS_EXPECT are valid\r
+///\r
+#define PTP_FIFO_STS_VALID BIT7\r
+///\r
+/// When this bit is 1, TPM is in the Ready state,\r
+/// indicating it is ready to receive a new command.\r
+///\r
+#define PTP_FIFO_STS_READY BIT6\r
+///\r
+/// Write a 1 to this bit to cause the TPM to execute that command.\r
+///\r
+#define PTP_FIFO_STS_GO BIT5\r
+///\r
+/// This bit indicates that the TPM has data available as a response.\r
+///\r
+#define PTP_FIFO_STS_DATA BIT4\r
+///\r
+/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
+///\r
+#define PTP_FIFO_STS_EXPECT BIT3\r
+///\r
+/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
+///\r
+#define PTP_FIFO_STS_SELFTEST_DONE BIT2\r
+///\r
+/// Writes a 1 to this bit to force the TPM to re-send the response.\r
+///\r
+#define PTP_FIFO_STS_RETRY BIT1\r
+\r
+///\r
+/// TPM Family Identifier.\r
+/// 00: TPM 1.2 Family\r
+/// 01: TPM 2.0 Family\r
+///\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)\r
+///\r
+/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r
+/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r
+///\r
+#define PTP_FIFO_STS_EX_CANCEL BIT0\r
+\r
+\r
+//\r
+// PTP CRB definition\r
+//\r
+\r
+//\r
+// Set structure alignment to 1-byte\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// Register set map as specified in PTP specification Chapter 5\r
+//\r
+typedef struct {\r
+ ///\r
+ /// Used to determine current state of Locality of the TPM.\r
+ ///\r
+ UINT32 LocalityState; // 0\r
+ UINT8 Reserved1[4]; // 4\r
+ ///\r
+ /// Used to gain control of the TPM by this Locality.\r
+ ///\r
+ UINT32 LocalityControl; // 8\r
+ ///\r
+ /// Used to determine whether Locality has been granted or Seized.\r
+ ///\r
+ UINT32 LocalityStatus; // 0ch\r
+ UINT8 Reserved2[0x20]; // 10h\r
+ ///\r
+ /// Used to identify the Interface types supported by the TPM.\r
+ ///\r
+ UINT32 InterfaceId; // 30h\r
+ ///\r
+ /// Vendor ID\r
+ ///\r
+ UINT16 Vid; // 34h\r
+ ///\r
+ /// Device ID\r
+ ///\r
+ UINT16 Did; // 36h\r
+ ///\r
+ /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r
+ ///\r
+ UINT64 CrbControlExtension; // 38h\r
+ ///\r
+ /// Register used to initiate transactions for the CRB interface.\r
+ ///\r
+ UINT32 CrbControlRequest; // 40h\r
+ ///\r
+ /// Register used by the TPM to provide status of the CRB interface.\r
+ ///\r
+ UINT32 CrbControlStatus; // 44h\r
+ ///\r
+ /// Register used by software to cancel command processing.\r
+ ///\r
+ UINT32 CrbControlCancel; // 48h\r
+ ///\r
+ /// Register used to indicate presence of command or response data in the CRB buffer.\r
+ ///\r
+ UINT32 CrbControlStart; // 4Ch\r
+ ///\r
+ /// Register used to configure and respond to interrupts.\r
+ ///\r
+ UINT32 CrbInterruptEnable; // 50h\r
+ UINT32 CrbInterruptStatus; // 54h\r
+ ///\r
+ /// Size of the Command buffer.\r
+ ///\r
+ UINT32 CrbControlCommandSize; // 58h\r
+ ///\r
+ /// Command buffer start address\r
+ ///\r
+ UINT32 CrbControlCommandAddressLow; // 5Ch\r
+ UINT32 CrbControlCommandAddressHigh; // 60h\r
+ ///\r
+ /// Size of the Response buffer\r
+ ///\r
+ UINT32 CrbControlResponseSize; // 64h\r
+ ///\r
+ /// Address of the start of the Response buffer\r
+ ///\r
+ UINT64 CrbControlResponseAddrss; // 68h\r
+ UINT8 Reserved4[0x10]; // 70h\r
+ ///\r
+ /// Command/Response Data may be defined as large as 3968 (0xF80).\r
+ ///\r
+ UINT8 CrbDataBuffer[0xF80]; // 80h\r
+} PTP_CRB_REGISTERS;\r
+\r
+//\r
+// Define pointer types used to access CRB registers on PTP\r
+//\r
+typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r
+\r
+//\r
+// Define bits of CRB Interface Identifier Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 InterfaceType:4;\r
+ UINT32 InterfaceVersion:4;\r
+ UINT32 CapLocality:1;\r
+ UINT32 Reserved1:2;\r
+ UINT32 CapDataXferSizeSupport:2;\r
+ UINT32 CapFIFO:1;\r
+ UINT32 CapCRB:1;\r
+ UINT32 CapIFRes:2;\r
+ UINT32 InterfaceSelector:2;\r
+ UINT32 IntfSelLock:1;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Rid:8;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PTP_CRB_INTERFACE_IDENTIFIER;\r
+\r
+///\r
+/// InterfaceType\r
+///\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF\r
+\r
+///\r
+/// InterfaceVersion\r
+///\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1\r
+\r
+///\r
+/// InterfaceSelector\r
+///\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0\r
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1\r
+\r
+//\r
+// Define bits of Locality State Register\r
+//\r
+\r
+///\r
+/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r
+///\r
+#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7\r
+\r
+///\r
+/// 000 - Locality 0\r
+/// 001 - Locality 1\r
+/// 010 - Locality 2\r
+/// 011 - Locality 3\r
+/// 100 - Locality 4\r
+///\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)\r
+\r
+///\r
+/// A 0 indicates to the host that no locality is assigned.\r
+/// A 1 indicates a locality has been assigned.\r
+///\r
+#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1\r
+\r
+///\r
+/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r
+/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r
+///\r
+#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0\r
+\r
+//\r
+// Define bits of Locality Control Register\r
+//\r
+\r
+///\r
+/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.\r
+///\r
+#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3\r
+\r
+///\r
+/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r
+///\r
+#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2\r
+\r
+///\r
+/// Writes (1): The active Locality is done with the TPM.\r
+///\r
+#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1\r
+\r
+///\r
+/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r
+///\r
+#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0\r
+\r
+//\r
+// Define bits of Locality Status Register\r
+//\r
+\r
+///\r
+/// 0: A higher locality has not initiated a Seize arbitration process.\r
+/// 1: A higher locality has Seized the TPM from this locality.\r
+///\r
+#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1\r
+\r
+///\r
+/// 0: Locality has not been granted to the TPM.\r
+/// 1: Locality has been granted access to the TPM\r
+///\r
+#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0\r
+\r
+//\r
+// Define bits of CRB Control Area Request Register\r
+//\r
+\r
+///\r
+/// Used by Software to indicate transition the TPM to and from the Idle state\r
+/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle\r
+/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r
+/// TPM SHALL complete this transition within TIMEOUT_C.\r
+///\r
+#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1\r
+\r
+///\r
+/// Used by Software to request the TPM transition to the Ready State.\r
+/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.\r
+/// 0: Cleared to 0 by TPM to acknowledge the request.\r
+/// TPM SHALL complete this transition within TIMEOUT_C.\r
+///\r
+#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0\r
+\r
+//\r
+// Define bits of CRB Control Area Status Register\r
+//\r
+\r
+///\r
+/// Used by TPM to indicate it is in the Idle State\r
+/// 1: Set by TPM when in the Idle State\r
+/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r
+/// SHALL be cleared by TIMEOUT_C.\r
+///\r
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1\r
+\r
+///\r
+/// Used by the TPM to indicate current status.\r
+/// 1: Set by TPM to indicate a FATAL Error\r
+/// 0: Indicates TPM is operational\r
+///\r
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0\r
+\r
+//\r
+// Define bits of CRB Control Cancel Register\r
+//\r
+\r
+///\r
+/// Used by software to cancel command processing Reads return correct value\r
+/// Writes (0000 0001h): Cancel a command\r
+/// Writes (0000 0000h): Clears field when command has been cancelled\r
+///\r
+#define PTP_CRB_CONTROL_CANCEL BIT0\r
+\r
+//\r
+// Define bits of CRB Control Start Register\r
+//\r
+\r
+///\r
+/// When set by software, indicates a command is ready for processing.\r
+/// Writes (0000 0001h): TPM transitions to Command Execution\r
+/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r
+///\r
+#define PTP_CRB_CONTROL_START BIT0\r
+\r
+//\r
+// Restore original structure alignment\r
+//\r
+#pragma pack ()\r
+\r
+//\r
+// Default TimeOut value\r
+//\r
+#define PTP_TIMEOUT_A (750 * 1000) // 750ms\r
+#define PTP_TIMEOUT_B (2000 * 1000) // 2s\r
+#define PTP_TIMEOUT_C (200 * 1000) // 200ms\r
+#define PTP_TIMEOUT_D (30 * 1000) // 30ms\r
+\r
+#endif
\ No newline at end of file
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