--- /dev/null
+/** @file\r
+ Main PAL API's defined in IPF PAL Spec.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: PalApi.h\r
+\r
+**/\r
+\r
+#ifndef __PAL_API_H__\r
+#define __PAL_API_H__\r
+\r
+//\r
+// IPF Specific Functions\r
+//\r
+\r
+typedef struct {\r
+ UINT64 Status;\r
+ UINT64 r9;\r
+ UINT64 r10;\r
+ UINT64 r11;\r
+} PAL_CALL_RETURN;\r
+\r
+\r
+\r
+//\r
+// CacheType of PAL_CACHE_FLUSH.\r
+//\r
+#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
+#define PAL_CACHE_FLUSH_DATA_ALL 2\r
+#define PAL_CACHE_FLUSH_ALL 3\r
+#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
+\r
+\r
+//\r
+// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
+// \r
+#define PAL_CACHE_FLUSH_INVIDED_LINES BIT0\r
+#define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1\r
+\r
+/**\r
+ \r
+ Flush the instruction or data caches. It is required by IPF.\r
+ The PAL procedure supports the Static Registers calling\r
+ convention. It could be called at virtual mode and physical\r
+ mode.\r
+\r
+ @param Index Index of PAL_CACHE_FLUSH within the\r
+ list of PAL procedures.\r
+ \r
+ @param CacheType Unsigned 64-bit integer indicating\r
+ which cache to flush.\r
+\r
+ @param Operation Formatted bit vector indicating the\r
+ operation of this call.\r
+\r
+ @param ProgressIndicator Unsigned 64-bit integer specifying\r
+ the starting position of the flush\r
+ operation.\r
+ \r
+ @return R9 Unsigned 64-bit integer specifying the vector\r
+ number of the pending interrupt.\r
+ \r
+ @return R10 Unsigned 64-bit integer specifying the\r
+ starting position of the flush operation.\r
+ \r
+ @return R11 Unsigned 64-bit integer specifying the vector\r
+ number of the pending interrupt.\r
+ \r
+ @return Status 2 - Call completed without error, but a PMI\r
+ was taken during the execution of this\r
+ procedure.\r
+\r
+ @return Status 1 - Call has not completed flushing due to\r
+ a pending interrupt.\r
+\r
+ @return Status 0 - Call completed without error\r
+\r
+ @return Status -2 - Invalid argument\r
+\r
+ @return Status -3 - Call completed with error\r
+ \r
+**/\r
+#define PAL_CACHE_FLUSH 1\r
+\r
+\r
+//\r
+// Attributes of PAL_CACHE_CONFIG_INFO1\r
+// \r
+#define PAL_CACHE_ATTR_WT 0\r
+#define PAL_CACHE_ATTR_WB 1\r
+\r
+//\r
+// PAL_CACHE_CONFIG_INFO1.StoreHint\r
+// \r
+#define PAL_CACHE_STORE_TEMPORAL 0\r
+#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
+\r
+//\r
+// PAL_CACHE_CONFIG_INFO1.StoreHint\r
+// \r
+#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
+#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
+\r
+//\r
+// PAL_CACHE_CONFIG_INFO1.StoreHint\r
+// \r
+#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
+#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
+#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
+\r
+//\r
+// Detail the characteristics of a given processor controlled\r
+// cache in the cache hierarchy.\r
+// \r
+typedef struct {\r
+ UINT64 IsUnified : 1;\r
+ UINT64 Attributes : 2;\r
+ UINT64 Associativity:8;\r
+ UINT64 LineSize:8;\r
+ UINT64 Stride:8;\r
+ UINT64 StoreLatency:8;\r
+ UINT64 StoreHint:8;\r
+ UINT64 LoadHint:8;\r
+} PAL_CACHE_INFO_RETURN1;\r
+\r
+//\r
+// Detail the characteristics of a given processor controlled\r
+// cache in the cache hierarchy.\r
+// \r
+typedef struct {\r
+ UINT64 CacheSize:32;\r
+ UINT64 AliasBoundary:8;\r
+ UINT64 TagLsBits:8;\r
+ UINT64 TagMsBits:8;\r
+} PAL_CACHE_INFO_RETURN2;\r
+\r
+/**\r
+ \r
+ Return detailed instruction or data cache information. It is\r
+ required by IPF. The PAL procedure supports the Static\r
+ Registers calling convention. It could be called at virtual\r
+ mode and physical mode.\r
+ \r
+ @param Index Index of PAL_CACHE_INFO within the list of\r
+ PAL procedures.\r
+ \r
+ @param CacheLevel Unsigned 64-bit integer specifying the\r
+ level in the cache hierarchy for which\r
+ information is requested. This value must\r
+ be between 0 and one less than the value\r
+ returned in the cache_levels return value\r
+ from PAL_CACHE_SUMMARY.\r
+ \r
+ @param CacheType Unsigned 64-bit integer with a value of 1\r
+ for instruction cache and 2 for data or\r
+ unified cache. All other values are\r
+ reserved.\r
+ \r
+ @param Reserved Should be 0.\r
+ \r
+ \r
+ @return R9 Detail the characteristics of a given\r
+ processor controlled cache in the cache\r
+ hierarchy. See PAL_CACHE_INFO_RETURN1.\r
+ \r
+ @return R10 Detail the characteristics of a given\r
+ processor controlled cache in the cache\r
+ hierarchy. See PAL_CACHE_INFO_RETURN2.\r
+ \r
+ @return R11 Reserved with 0.\r
+ \r
+ \r
+ @return Status 0 - Call completed without error\r
+\r
+ @return Status -2 - Invalid argument\r
+\r
+ @return Status -3 - Call completed with error\r
+ \r
+**/\r
+#define PAL_CACHE_INFO 2\r
+\r
+\r
+\r
+//\r
+// Level of PAL_CACHE_INIT.\r
+// \r
+#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
+\r
+//\r
+// Restrict of PAL_CACHE_INIT.\r
+// \r
+#define PAL_CACHE_INIT_NO_RESTRICT 0\r
+#define PAL_CACHE_INIT_RESTRICTED 1\r
+\r
+/**\r
+ \r
+ Initialize the instruction or data caches. It is required by\r
+ IPF. The PAL procedure supports the Static Registers calling\r
+ convention. It could be called at physical mode.\r
+\r
+ @param Index Index of PAL_CACHE_INIT within the list of PAL\r
+ procedures.\r
+ \r
+ @param Level Unsigned 64-bit integer containing the level of\r
+ cache to initialize. If the cache level can be\r
+ initialized independently, only that level will\r
+ be initialized. Otherwise\r
+ implementation-dependent side-effects will\r
+ occur.\r
+ \r
+ @param CacheType Unsigned 64-bit integer with a value of 1 to\r
+ initialize the instruction cache, 2 to\r
+ initialize the data cache, or 3 to\r
+ initialize both. All other values are\r
+ reserved.\r
+\r
+ @param Restrict Unsigned 64-bit integer with a value of 0 or\r
+ 1. All other values are reserved. If\r
+ restrict is 1 and initializing the specified\r
+ level and cache_type of the cache would\r
+ cause side-effects, PAL_CACHE_INIT will\r
+ return -4 instead of initializing the cache.\r
+ \r
+ \r
+ @return Status 0 - Call completed without error\r
+\r
+ @return Status -2 - Invalid argument\r
+\r
+ @return Status -3 - Call completed with error.\r
+ \r
+ @return Status -4 - Call could not initialize the specified\r
+ level and cache_type of the cache without\r
+ side-effects and restrict was 1. \r
+ \r
+**/\r
+#define PAL_CACHE_INIT 3 \r
+\r
+\r
+//\r
+// PAL_CACHE_PROTECTION.Method.\r
+// \r
+#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
+#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
+#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
+#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
+\r
+\r
+\r
+//\r
+// PAL_CACHE_PROTECTION.TagOrData.\r
+// \r
+#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
+#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
+#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
+#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
+\r
+//\r
+// 32-bit protection information structures.\r
+// \r
+typedef struct {\r
+ UINT32 DataBits:8;\r
+ UINT32 TagProtLsb:6;\r
+ UINT32 TagProtMsb:6;\r
+ UINT32 ProtBits:6;\r
+ UINT32 Method:4;\r
+ UINT32 TagOrData:2;\r
+} PAL_CACHE_PROTECTION;\r
+\r
+/**\r
+ \r
+ Return instruction or data cache protection information. It is\r
+ required by IPF. The PAL procedure supports the Static\r
+ Registers calling convention. It could be called at physical\r
+ mode and Virtual mode.\r
+\r
+ @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
+ PAL procedures.\r
+\r
+ @param CacheLevel Unsigned 64-bit integer specifying the level\r
+ in the cache hierarchy for which information\r
+ is requested. This value must be between 0\r
+ and one less than the value returned in the\r
+ cache_levels return value from\r
+ PAL_CACHE_SUMMARY.\r
+\r
+ @param CacheType Unsigned 64-bit integer with a value of 1\r
+ for instruction cache and 2 for data or\r
+ unified cache. All other values are\r
+ reserved.\r
+ \r
+ @return R9 Detail the characteristics of a given\r
+ processor controlled cache in the cache\r
+ hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
+ \r
+ @return R10 Detail the characteristics of a given\r
+ processor controlled cache in the cache\r
+ hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
+ \r
+ @return R11 Detail the characteristics of a given\r
+ processor controlled cache in the cache\r
+ hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
+ \r
+ \r
+ @return Status 0 - Call completed without error\r
+\r
+ @return Status -2 - Invalid argument\r
+\r
+ @return Status -3 - Call completed with error.\r
+ \r
+**/\r
+#define PAL_CACHE_PROT_INFO 38\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+///\r
+// ?????????\r
+\r
+\r
+\r
+/**\r
+ \r
+ Returns information on which logical processors share caches.\r
+ It is optional.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_CACHE_SHARED_INFO 43\r
+\r
+\r
+/**\r
+ \r
+ Return a summary of the cache hierarchy. It is required by\r
+ IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_CACHE_SUMMARY 4\r
+\r
+/**\r
+ \r
+ Return a list of supported memory attributes.. It is required\r
+ by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_MEM_ATTRIB 5\r
+\r
+/**\r
+ \r
+ Used in architected sequence to transition pages from a\r
+ cacheable, speculative attribute to an uncacheable attribute.\r
+ It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_PREFETCH_VISIBILITY 41\r
+\r
+/**\r
+ \r
+ Return information needed for ptc.e instruction to purge\r
+ entire TC. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_PTCE_INFO 6\r
+\r
+/**\r
+ \r
+ Return detailed information about virtual memory features\r
+ supported in the processor. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_VM_INFO 7\r
+\r
+\r
+/**\r
+ \r
+ Return virtual memory TC and hardware walker page sizes\r
+ supported in the processor. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_VM_PAGE_SIZE 34\r
+\r
+/**\r
+ \r
+ Return summary information about virtual memory features\r
+ supported in the processor. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_VM_SUMMARY 8\r
+\r
+/**\r
+ \r
+ Read contents of a translation register. It is required by\r
+ IPF.\r
+\r
+ @param CallingConvention Stacked Register\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_VM_TR_READ 261 \r
+\r
+/**\r
+ \r
+ Return configurable processor bus interface features and their\r
+ current settings. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_BUS_GET_FEATURES 9\r
+\r
+\r
+/**\r
+ \r
+ Enable or disable configurable features in processor bus\r
+ interface. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_BUS_SET_FEATURES 10\r
+\r
+\r
+/**\r
+ \r
+ Return the number of instruction and data breakpoint\r
+ registers. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_DEBUG_INFO 11\r
+\r
+/**\r
+ \r
+ Return the fixed component of a processor¡¯s directed address.\r
+ It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_FIXED_ADDR 12\r
+\r
+/**\r
+ \r
+ Return the frequency of the output clock for use by the\r
+ platform, if generated by the processor. It is optinal.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_FREQ_BASE 13\r
+\r
+/**\r
+ \r
+ Return ratio of processor, bus, and interval time counter to\r
+ processor input clock or output clock for platform use, if\r
+ generated by the processor. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_FREQ_RATIOS 14\r
+\r
+/**\r
+ \r
+ Return information on which logical processors map to a\r
+ physical processor die. It is optinal.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_LOGICAL_TO_PHYSICAL 42\r
+\r
+/**\r
+ \r
+ Return the number and type of performance monitors. It is\r
+ required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_PERF_MON_INFO 15\r
+\r
+/**\r
+ \r
+ Specify processor interrupt block address and I/O port space\r
+ address. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_PLATFORM_ADDR 16\r
+\r
+\r
+/**\r
+ \r
+ Return configurable processor features and their current\r
+ setting. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_PROC_GET_FEATURES 17\r
+\r
+\r
+/**\r
+ \r
+ Enable or disable configurable processor features. It is\r
+ required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_PROC_SET_FEATURES 18\r
+\r
+/**\r
+ \r
+ Return AR and CR register information. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_REGISTER_INFO 39 \r
+\r
+/**\r
+ \r
+ Return RSE information. It is required by\r
+ IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_RSE_INFO 19\r
+\r
+/**\r
+ \r
+ Return version of PAL code. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_VERSION 20\r
+\r
+/**\r
+ \r
+ Clear all error information from processor error logging\r
+ registers. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_MC_CLEAR_LOG 21 \r
+\r
+/**\r
+ \r
+ Ensure that all operations that could cause an MCA have\r
+ completed. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_MC_DRAIN 22\r
+\r
+/**\r
+ \r
+ Return Processor Dynamic State for logging by SAL. It is\r
+ optional.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_MC_DYNAMIC_STATE 24 \r
+\r
+/**\r
+ \r
+ Return Processor Machine Check Information and Processor\r
+ Static State for logging by SAL. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_MC_ERROR_INFO 25 Req. Static Both \r
+\r
+/**\r
+ \r
+ Set/Reset Expected Machine Check Indicator. It is required by\r
+ IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_MC_EXPECTED 23 \r
+\r
+/**\r
+ \r
+ Register min-state save area with PAL for machine checks and\r
+ inits. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_MC_REGISTER_MEM 27 \r
+\r
+/**\r
+ \r
+ Restore minimal architected state and return to interrupted\r
+ process. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_MC_RESUME 26 \r
+\r
+/**\r
+ \r
+ Enter the low-power HALT state or an implementation-dependent\r
+ low-power state. It is optinal.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_HALT 28\r
+\r
+\r
+/**\r
+ \r
+ Return the low power capabilities of the processor. It is\r
+ required by IPF.\r
+\r
+ @param CallingConvention Stacked Register\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_HALT_INFO 257\r
+\r
+\r
+/**\r
+ \r
+ Enter the low power LIGHT HALT state. It is required by\r
+ IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical/Virtual\r
+ \r
+**/\r
+#define PAL_HALT_LIGHT 29 \r
+\r
+/**\r
+ \r
+ Initialize tags and data of a cache line for processor\r
+ testing. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_CACHE_LINE_INIT 31\r
+\r
+/**\r
+ \r
+ Read tag and data of a cache line for diagnostic testing. It\r
+ is optional.\r
+\r
+ @param CallingConvention Satcked Register\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_CACHE_READ 259 \r
+\r
+/**\r
+ \r
+ Write tag and data of a cache for diagnostic testing. It is\r
+ optional.\r
+\r
+ @param CallingConvention Satcked Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_CACHE_WRITE 260\r
+\r
+/**\r
+ \r
+ Returns alignment and size requirements needed for the memory\r
+ buffer passed to the PAL_TEST_PROC procedure as well as\r
+ information on self-test control words for the processor self\r
+ tests. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_TEST_INFO 37\r
+\r
+/**\r
+ \r
+ Perform late processor self test. It is required by\r
+ IPF.\r
+\r
+ @param CallingConvention Stacked Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_TEST_PROC 258\r
+\r
+/**\r
+ \r
+ Return information needed to relocate PAL procedures and PAL\r
+ PMI code to memory. It is required by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_COPY_INFO 30\r
+\r
+/**\r
+ \r
+ Relocate PAL procedures and PAL PMI code to memory. It is\r
+ required by IPF.\r
+\r
+ @param CallingConvention Stacked Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_COPY_PAL 256\r
+\r
+/**\r
+ \r
+ Enter IA-32 System environment. It is optional.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_ENTER_IA_32_ENV 33\r
+\r
+/**\r
+ \r
+ Register PMI memory entrypoints with processor. It is required\r
+ by IPF.\r
+\r
+ @param CallingConvention Static Registers\r
+\r
+ @param Mode Physical\r
+ \r
+**/\r
+#define PAL_PMI_ENTRYPOINT 32\r
+\r
+\r
+\r
+#endif\r
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