IN CONST CHAR16 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the length of a Null-terminated Unicode string.\r
IN CONST CHAR16 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the first occurrence of a Null-terminated Unicode sub-string\r
OUT CHAR8 *Destination\r
);\r
\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Convert a Null-terminated Unicode string to a Null-terminated\r
IN CONST CHAR8 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the length of a Null-terminated ASCII string.\r
IN CONST CHAR8 *Source,\r
IN UINTN Length\r
);\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Returns the first occurrence of a Null-terminated ASCII sub-string\r
OUT CHAR16 *Destination\r
);\r
\r
-#endif\r
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)\r
\r
/**\r
Convert one Null-terminated ASCII string to a Null-terminated\r
@retval 0 Indicates a return from SetJump().\r
\r
**/\r
+RETURNS_TWICE\r
UINTN\r
EFIAPI\r
SetJump (\r
IN UINT64 Arg3,\r
IN UINT64 Arg4\r
);\r
-#endif\r
+#endif // defined (MDE_CPU_IPF)\r
\r
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
\r
+#define IA32_GDT_TYPE_TSS 0x9\r
+#define IA32_GDT_ALIGNMENT 8\r
\r
#if defined (MDE_CPU_IA32)\r
///\r
UINT64 Uint64;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
-#endif\r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+ UINT16 PreviousTaskLink;\r
+ UINT16 Reserved_2;\r
+ UINT32 ESP0;\r
+ UINT16 SS0;\r
+ UINT16 Reserved_10;\r
+ UINT32 ESP1;\r
+ UINT16 SS1;\r
+ UINT16 Reserved_18;\r
+ UINT32 ESP2;\r
+ UINT16 SS2;\r
+ UINT16 Reserved_26;\r
+ UINT32 CR3;\r
+ UINT32 EIP;\r
+ UINT32 EFLAGS;\r
+ UINT32 EAX;\r
+ UINT32 ECX;\r
+ UINT32 EDX;\r
+ UINT32 EBX;\r
+ UINT32 ESP;\r
+ UINT32 EBP;\r
+ UINT32 ESI;\r
+ UINT32 EDI;\r
+ UINT16 ES;\r
+ UINT16 Reserved_74;\r
+ UINT16 CS;\r
+ UINT16 Reserved_78;\r
+ UINT16 SS;\r
+ UINT16 Reserved_82;\r
+ UINT16 DS;\r
+ UINT16 Reserved_86;\r
+ UINT16 FS;\r
+ UINT16 Reserved_90;\r
+ UINT16 GS;\r
+ UINT16 Reserved_94;\r
+ UINT16 LDTSegmentSelector;\r
+ UINT16 Reserved_98;\r
+ UINT16 T;\r
+ UINT16 IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow:16; ///< Segment Limit 15..00\r
+ UINT32 BaseLow:16; ///< Base Address 15..00\r
+ UINT32 BaseMid:8; ///< Base Address 23..16\r
+ UINT32 Type:4; ///< Type (1 0 B 1)\r
+ UINT32 Reserved_43:1; ///< 0\r
+ UINT32 DPL:2; ///< Descriptor Privilege Level\r
+ UINT32 P:1; ///< Segment Present\r
+ UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
+ UINT32 AVL:1; ///< Available for use by system software\r
+ UINT32 Reserved_52:2; ///< 0 0\r
+ UINT32 G:1; ///< Granularity\r
+ UINT32 BaseHigh:8; ///< Base Address 31..24\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_TSS_DESCRIPTOR;\r
+#pragma pack ()\r
+\r
+#endif // defined (MDE_CPU_IA32)\r
\r
#if defined (MDE_CPU_X64)\r
///\r
} Uint128; \r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
-#endif\r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+ UINT32 Reserved_0;\r
+ UINT64 RSP0;\r
+ UINT64 RSP1;\r
+ UINT64 RSP2;\r
+ UINT64 Reserved_28;\r
+ UINT64 IST[7];\r
+ UINT64 Reserved_92;\r
+ UINT16 Reserved_100;\r
+ UINT16 IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow:16; ///< Segment Limit 15..00\r
+ UINT32 BaseLow:16; ///< Base Address 15..00\r
+ UINT32 BaseMidl:8; ///< Base Address 23..16\r
+ UINT32 Type:4; ///< Type (1 0 B 1)\r
+ UINT32 Reserved_43:1; ///< 0\r
+ UINT32 DPL:2; ///< Descriptor Privilege Level\r
+ UINT32 P:1; ///< Segment Present\r
+ UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
+ UINT32 AVL:1; ///< Available for use by system software\r
+ UINT32 Reserved_52:2; ///< 0 0\r
+ UINT32 G:1; ///< Granularity\r
+ UINT32 BaseMidh:8; ///< Base Address 31..24\r
+ UINT32 BaseHigh:32; ///< Base Address 63..32\r
+ UINT32 Reserved_96:32; ///< Reserved\r
+ } Bits;\r
+ struct {\r
+ UINT64 Uint64;\r
+ UINT64 Uint64_1;\r
+ } Uint128;\r
+} IA32_TSS_DESCRIPTOR;\r
+#pragma pack ()\r
+\r
+#endif // defined (MDE_CPU_X64)\r
\r
///\r
/// Byte packed structure for an FP/SSE/SSE2 context.\r
#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\r
#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\r
\r
+///\r
+/// Type definition for representing labels in NASM source code that allow for\r
+/// the patching of immediate operands of IA32 and X64 instructions.\r
+///\r
+/// While the type is technically defined as a function type (note: not a\r
+/// pointer-to-function type), such labels in NASM source code never stand for\r
+/// actual functions, and identifiers declared with this function type should\r
+/// never be called. This is also why the EFIAPI calling convention specifier\r
+/// is missing from the typedef, and why the typedef does not follow the usual\r
+/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID\r
+/// return type and the VOID argument list are merely artifacts.\r
+///\r
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);\r
+\r
/**\r
Retrieves CPUID information.\r
\r
OUT UINT64 *Rand\r
);\r
\r
-#endif\r
-#endif\r
+/**\r
+ Load given selector into TR register.\r
\r
+ @param[in] Selector Task segment selector\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteTr (\r
+ IN UINT16 Selector\r
+ );\r
+\r
+/**\r
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
+ word, dword or qword operand is encoded at the end of the instruction's\r
+ binary representation.\r
+\r
+ This function should be used to update object code that was compiled with\r
+ NASM from assembly source code. Example:\r
+\r
+ NASM source code:\r
+\r
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched\r
+ ASM_PFX(gPatchCr3):\r
+ mov cr3, eax\r
+\r
+ C source code:\r
+\r
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r
+\r
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The\r
+ immediate operand to patch is expected to\r
+ comprise the trailing bytes of the instruction.\r
+ If InstructionEnd is closer to address 0 than\r
+ ValueSize permits, then ASSERT().\r
+\r
+ @param[in] PatchValue The constant to write to the immediate operand.\r
+ The caller is responsible for ensuring that\r
+ PatchValue can be represented in the byte, word,\r
+ dword or qword operand (as indicated through\r
+ ValueSize); otherwise ASSERT().\r
+\r
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r
+ 4, or 8. ASSERT() otherwise.\r
+**/\r
+VOID\r
+EFIAPI\r
+PatchInstructionX86 (\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
+ );\r
\r
+#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+#endif // !defined (__BASE_LIB__)\r
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