Second set of changes based on a review of the code comments in the Include directory...

[mirror_edk2.git] / MdePkg / Include / Library / CacheMaintenanceLib.h

diff --git a/MdePkg/Include/Library/CacheMaintenanceLib.h b/MdePkg/Include/Library/CacheMaintenanceLib.h
index a575ec2fc1f9db1e8d07860c275d9c43826a2a81..eec7745123d6093862535e15e66a2c77efc931a9 100644 (file)
--- a/MdePkg/Include/Library/CacheMaintenanceLib.h
+++ b/MdePkg/Include/Library/CacheMaintenanceLib.h
@@ -39,7 +39,7 @@ InvalidateInstructionCache (
   aligned on a cache line boundary, then the entire instruction cache line\r
   containing Address + Length -1 is invalidated. This function may choose to\r
   invalidate the entire instruction cache if that is more efficient than\r
-  invalidating the specified range. If Length is 0, the no instruction cache\r
+  invalidating the specified range. If Length is 0, then no instruction cache\r
   lines are invalidated. Address is returned.\r
 \r
   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
@@ -88,7 +88,7 @@ WriteBackInvalidateDataCache (
   line containing Address + Length -1 is written back and invalidated. This\r
   function may choose to write back and invalidate the entire data cache if\r
   that is more efficient than writing back and invalidating the specified\r
-  range. If Length is 0, the no data cache lines are written back and\r
+  range. If Length is 0, then no data cache lines are written back and\r
   invalidated. Address is returned.\r
 \r
   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
@@ -136,7 +136,7 @@ WriteBackDataCache (
   cache line boundary, then the entire data cache line containing Address +\r
   Length -1 is written back. This function may choose to write back the entire\r
   data cache if that is more efficient than writing back the specified range.\r
-  If Length is 0, the no data cache lines are written back. This function may\r
+  If Length is 0, then no data cache lines are written back. This function may\r
   also invalidate all the data cache lines in the specified range of the cache\r
   coherency domain of the calling CPU. Address is returned.\r
 \r