address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r
The layout of this address parameter is as follows:\r
\r
- PCI Register: Bits 0..11\r
- PCI Function Bits 12..14\r
- PCI Device Bits 15..19\r
- PCI Bus Bits 20..27\r
- Reserved Bits 28..31. Must be 0.\r
- PCI Segment Bits 32..47\r
- Reserved Bits 48..63. Must be 0.\r
+ PCI Register: Bits 0..11\r
+ PCI Function Bits 12..14\r
+ PCI Device Bits 15..19\r
+ PCI Bus Bits 20..27\r
+ Reserved Bits 28..31. Must be 0.\r
+ PCI Segment Bits 32..47\r
+ Reserved Bits 48..63. Must be 0.\r
\r
| Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r
63 48 47 32 31 28 27 20 19 15 14 12 11 0\r
access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
accesses when PCI Segments other than Segment #0 must be accessed. \r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
**/\r
#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
- ( ((Register) & 0xfff) | \\r
- (((Function) & 0x07) << 12) | \\r
- (((Device) & 0x1f) << 15) | \\r
- (((Bus) & 0xff) << 20) | \\r
- (LShiftU64((Segment) & 0xffff, 32)) \\r
+ ((Segment != 0) ? \\r
+ ( ((Register) & 0xfff) | \\r
+ (((Function) & 0x07) << 12) | \\r
+ (((Device) & 0x1f) << 15) | \\r
+ (((Bus) & 0xff) << 20) | \\r
+ (LShiftU64 ((Segment) & 0xffff, 32)) \\r
+ ) : \\r
+ ( ((Register) & 0xfff) | \\r
+ (((Function) & 0x07) << 12) | \\r
+ (((Device) & 0x1f) << 15) | \\r
+ (((Bus) & 0xff) << 20) \\r
+ ) \\r
)\r
\r
/**\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
- followed a bitwise inclusive OR with another 8-bit value.\r
+ followed a bitwise OR with another 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
writes the result back to the bit field in the 8-bit port.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 8-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
\r
/**\r
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
8-bit port.\r
\r
Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
+ bitwise AND followed by a bitwise OR between the read result and\r
the value specified by AndData, and writes the result to the 8-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r
+ Performs a bitwise OR of a 16-bit PCI configuration register with\r
a 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 16-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
- followed a bitwise inclusive OR with another 16-bit value.\r
+ followed a bitwise OR with another 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
\r
/**\r
Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address. \r
\r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
and writes the result back to the bit field in the 16-bit port.\r
\r
Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
\r
/**\r
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
16-bit port.\r
\r
Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
+ bitwise AND followed by a bitwise OR between the read result and\r
the value specified by AndData, and writes the result to the 16-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
\r
Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
- followed a bitwise inclusive OR with another 32-bit value.\r
+ followed a bitwise OR with another 32-bit value.\r
\r
Reads the 32-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
writes the result back to the bit field in the 32-bit port.\r
\r
Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
+ bitwise OR between the read result and the value specified by\r
OrData, and writes the result to the 32-bit PCI configuration register\r
specified by Address. The value written to the PCI configuration register is\r
returned. This function must guarantee that all PCI read and write operations\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
- \r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
\r
/**\r
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
+ bitwise OR, and writes the result back to the bit field in the\r
32-bit port.\r
\r
Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
+ bitwise AND followed by a bitwise OR between the read result and\r
the value specified by AndData, and writes the result to the 32-bit PCI\r
configuration register specified by Address. The value written to the PCI\r
configuration register is returned. This function must guarantee that all PCI\r
If StartBit is greater than 31, then ASSERT().\r
If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
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