address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r
The layout of this address parameter is as follows:\r
\r
- PCI Register: Bits 0..11\r
- PCI Function Bits 12..14\r
- PCI Device Bits 15..19\r
- PCI Bus Bits 20..27\r
- Reserved Bits 28..31. Must be 0.\r
- PCI Segment Bits 32..47\r
- Reserved Bits 48..63. Must be 0.\r
+ PCI Register: Bits 0..11\r
+ PCI Function Bits 12..14\r
+ PCI Device Bits 15..19\r
+ PCI Bus Bits 20..27\r
+ Reserved Bits 28..31. Must be 0.\r
+ PCI Segment Bits 32..47\r
+ Reserved Bits 48..63. Must be 0.\r
\r
| Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r
63 48 47 32 31 28 27 20 19 15 14 12 11 0\r
access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
accesses when PCI Segments other than Segment #0 must be accessed. \r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
**/\r
#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
- ( ((Register) & 0xfff) | \\r
- (((Function) & 0x07) << 12) | \\r
- (((Device) & 0x1f) << 15) | \\r
- (((Bus) & 0xff) << 20) | \\r
- (LShiftU64((Segment) & 0xffff, 32)) \\r
+ ((Segment != 0) ? \\r
+ ( ((Register) & 0xfff) | \\r
+ (((Function) & 0x07) << 12) | \\r
+ (((Device) & 0x1f) << 15) | \\r
+ (((Bus) & 0xff) << 20) | \\r
+ (LShiftU64 ((Segment) & 0xffff, 32)) \\r
+ ) : \\r
+ ( ((Register) & 0xfff) | \\r
+ (((Function) & 0x07) << 12) | \\r
+ (((Device) & 0x1f) << 15) | \\r
+ (((Bus) & 0xff) << 20) \\r
+ ) \\r
)\r
\r
/**\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
- @return The parameter of Value.\r
+ @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
\r
/**\r
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
- followed a bitwise inclusive OR with another 8-bit value.\r
+ followed a bitwise OR with another 8-bit value.\r
\r
Reads the 8-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 8-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
/**\r
Reads a bit field of a PCI configuration register.\r
\r
- Reads the bit field in an 8-bit PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- The value of the bit field is returned.\r
- \r
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
+ Range 0..7.\r
\r
- @return The value of the bit field.\r
+ @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT8\r
/**\r
Writes a bit field to a PCI configuration register.\r
\r
- Writes Value to the bit field of the PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- All other bits in the destination PCI configuration register are preserved.\r
- The new value of the 8-bit register is returned.\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 8-bit register is returned.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
+ Range 0..7.\r
@param Value New value of the bit field.\r
\r
- @return The new value of the 8-bit register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
);\r
\r
/**\r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address. \r
- \r
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 8-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
+ Range 0..7.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
);\r
\r
/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 8-bit port.\r
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 8-bit register.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 8-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
\r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
- \r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
);\r
\r
/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r
- and writes the result back to the bit field in the 8-bit register.\r
- \r
- Reads the 8-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 8-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in AndData are stripped.\r
- \r
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 8-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..7.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r
+ Performs a bitwise OR of a 16-bit PCI configuration register with\r
+ a 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized.\r
\r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- \r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
\r
/**\r
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
- followed a bitwise inclusive OR with another 16-bit value.\r
+ followed a bitwise OR with another 16-bit value.\r
\r
Reads the 16-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
/**\r
Reads a bit field of a PCI configuration register.\r
\r
- Reads the bit field in a 16-bit PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- The value of the bit field is returned.\r
- \r
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
+ Range 0..15.\r
\r
- @return The value of the bit field.\r
+ @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT16\r
/**\r
Writes a bit field to a PCI configuration register.\r
\r
- Writes Value to the bit field of the PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- All other bits in the destination PCI configuration register are preserved.\r
- The new value of the 16-bit register is returned.\r
- \r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 16-bit register is returned.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
+ Range 0..15.\r
@param Value New value of the bit field.\r
\r
- @return The new value of the 16-bit register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
\r
/**\r
Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address. \r
\r
If any reserved bits in Address are set, then ASSERT().\r
If StartBit is greater than 15, then ASSERT().\r
If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
+ Range 0..15.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
and writes the result back to the bit field in the 16-bit port.\r
\r
Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 16-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
If StartBit is greater than 7, then ASSERT().\r
If EndBit is greater than 7, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
);\r
\r
/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r
- and writes the result back to the bit field in the 16-bit register.\r
- \r
- Reads the 16-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 16-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in AndData are stripped.\r
- \r
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 16-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT()..\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..15.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
);\r
\r
/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
\r
Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
\r
/**\r
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
- followed a bitwise inclusive OR with another 32-bit value.\r
+ followed a bitwise OR with another 32-bit value.\r
\r
Reads the 32-bit PCI configuration register specified by Address,\r
performs a bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
and writes the result to the 32-bit PCI configuration register specified by Address.\r
The value written to the PCI configuration register is returned.\r
This function must guarantee that all PCI read and write operations are serialized.\r
/**\r
Reads a bit field of a PCI configuration register.\r
\r
- Reads the bit field in a 32-bit PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- The value of the bit field is returned.\r
- \r
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to read.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
+ Range 0..31.\r
\r
- @return The value of the bit field.\r
+ @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT32\r
/**\r
Writes a bit field to a PCI configuration register.\r
\r
- Writes Value to the bit field of the PCI configuration register.\r
- The bit field is specified by the StartBit and the EndBit.\r
- All other bits in the destination PCI configuration register are preserved.\r
- The new value of the 32-bit register is returned.\r
- \r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 32-bit register is returned.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
+ Range 0..31.\r
@param Value New value of the bit field.\r
\r
- @return The new value of the 32-bit register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
);\r
\r
/**\r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address. \r
- \r
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 32-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
- \r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
);\r
\r
/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r
- and writes the result back to the bit field in the 32-bit port.\r
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 32-bit register.\r
\r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise inclusive OR between the read result and the value specified by OrData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in OrData are stripped.\r
\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
+ AND between the read result and the value specified by AndData, and writes the result\r
+ to the 32-bit PCI configuration register specified by Address. The value written to\r
+ the PCI configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in AndData are stripped.\r
If any reserved bits in Address are set, then ASSERT().\r
If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
);\r
\r
/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r
- and writes the result back to the bit field in the 32-bit register.\r
- \r
- Reads the 32-bit PCI configuration register specified by Address,\r
- performs a bitwise AND between the read result and the value specified by AndData,\r
- and writes the result to the 32-bit PCI configuration register specified by Address.\r
- The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are serialized.\r
- Extra left bits in AndData are stripped.\r
- \r
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 32-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
If any reserved bits in Address are set, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
- @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Address PCI configuration register to write.\r
@param StartBit The ordinal of the least significant bit in the bit field.\r
- The ordinal of the least significant bit in a byte is bit 0.\r
+ Range 0..31.\r
@param EndBit The ordinal of the most significant bit in the bit field.\r
- The ordinal of the most significant bit in a byte is bit 7.\r
- @param AndData The value to AND with the read value from the PCI configuration register.\r
- @param OrData The value to OR with the read value from the PCI configuration register.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
\r
- @return The value written to the PCI configuration register.\r
+ @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
/**\r
Reads a range of PCI configuration registers into a caller supplied buffer.\r
\r
- Reads the range of PCI configuration registers specified by StartAddress\r
- and Size into the buffer specified by Buffer.\r
- This function only allows the PCI configuration registers from a single PCI function to be read.\r
- Size is returned.\r
- \r
+ Reads the range of PCI configuration registers specified by StartAddress and\r
+ Size into the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be read. Size is\r
+ returned. When possible 32-bit PCI configuration read cycles are used to read\r
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+ end of the range.\r
+\r
If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer receiving the data read.\r
\r
- @return The parameter of Size.\r
+ @return Size\r
\r
**/\r
UINTN\r
);\r
\r
/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r
+ Copies the data in a caller supplied buffer to a specified range of PCI\r
+ configuration space.\r
+\r
+ Writes the range of PCI configuration registers specified by StartAddress and\r
+ Size from the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be written. Size is\r
+ returned. When possible 32-bit PCI configuration write cycles are used to\r
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+ and the end of the range.\r
\r
- Writes the range of PCI configuration registers specified by StartAddress\r
- and Size from the buffer specified by Buffer.\r
- This function only allows the PCI configuration registers from a single PCI function to be written.\r
- Size is returned.\r
- \r
If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
- If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r
- If Buffer is NULL, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
- @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
@param Size Size in bytes of the transfer.\r
@param Buffer Pointer to a buffer containing the data to write.\r
\r
projects / mirror_edk2.git / blobdiff