/** @file\r
StatusCode related definitions in PI.\r
\r
- Copyright (c) 2009, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved<BR>\r
+This program and the accompanying materials are licensed and made available under \r
+the terms and conditions of the BSD License that accompanies this distribution. \r
+The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php. \r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
@par Revision Reference:\r
- These status codes are defined in UEFI Platform Initialization Specification 1.2 \r
- Volume 3: Shared Architectural Elements\r
+ These status codes are defined in UEFI Platform Initialization Specification 1.2, \r
+ Volume 3: Shared Architectural Elements.\r
\r
**/\r
\r
#include <Protocol/DebugSupport.h>\r
\r
///\r
-/// Status Code Type Definition\r
+/// Status Code Type Definition.\r
///\r
typedef UINT32 EFI_STATUS_CODE_TYPE;\r
\r
///\r
-/// A Status Code Type is made up of the code type and severity\r
+/// A Status Code Type is made up of the code type and severity.\r
/// All values masked by EFI_STATUS_CODE_RESERVED_MASK are\r
/// reserved for use by this specification.\r
///\r
///@}\r
\r
///\r
-/// Definition of code types, all other values masked by\r
+/// Definition of code types. All other values masked by\r
/// EFI_STATUS_CODE_TYPE_MASK are reserved for use by\r
/// this specification.\r
///\r
/// EFI_STATUS_CODE_SEVERITY_MASK are reserved for use by\r
/// this specification.\r
/// Uncontained errors are major errors that could not contained\r
-/// to the specific component that is reporting the error\r
+/// to the specific component that is reporting the error.\r
/// For example, if a memory error was not detected early enough,\r
/// the bad data could be consumed by other drivers.\r
///\r
///@}\r
\r
///\r
-/// Status Code Value Definition\r
+/// Status Code Value Definition.\r
///\r
typedef UINT32 EFI_STATUS_CODE_VALUE;\r
\r
} EFI_STATUS_CODE_DATA;\r
\r
///\r
-/// General partitioning scheme for Progress and Error Codes are\r
-/// - 0x0000-0x0FFF Shared by all sub-classes in a given class\r
-/// - 0x1000-0x7FFF Subclass Specific\r
-/// - 0x8000-0xFFFF OEM specific\r
+/// General partitioning scheme for Progress and Error Codes are:\r
+/// - 0x0000-0x0FFF Shared by all sub-classes in a given class.\r
+/// - 0x1000-0x7FFF Subclass Specific.\r
+/// - 0x8000-0xFFFF OEM specific.\r
///@{\r
#define EFI_SUBCLASS_SPECIFIC 0x1000\r
#define EFI_OEM_SPECIFIC 0x8000\r
///@}\r
\r
///\r
-/// Debug Code definitions for all classes and subclass\r
+/// Debug Code definitions for all classes and subclass.\r
/// Only one debug code is defined at this point and should\r
-/// be used for anything that gets sent to debug stream.\r
+/// be used for anything that is sent to the debug stream.\r
///\r
///@{\r
#define EFI_DC_UNSPECIFIED 0x0\r
///@}\r
\r
///\r
-/// Class definitions\r
+/// Class definitions.\r
/// Values of 4-127 are reserved for future use by this specification.\r
/// Values in the range 127-255 are reserved for OEM use.\r
///\r
//\r
\r
///\r
-/// South Bridge initialization prior to memory detection\r
+/// South Bridge initialization prior to memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)\r
\r
///\r
-/// North Bridge initialization prior to memory detection\r
+/// North Bridge initialization prior to memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)\r
\r
///\r
-/// South Bridge initialization after memory detection\r
+/// South Bridge initialization after memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)\r
\r
///\r
-/// North Bridge initialization after memory detection\r
+/// North Bridge initialization after memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)\r
\r
///\r
-/// PCI Host Bridge DXE initialization\r
+/// PCI Host Bridge DXE initialization.\r
///\r
#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)\r
\r
///\r
-/// North Bridge DXE initialization\r
+/// North Bridge DXE initialization.\r
///\r
#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)\r
\r
///\r
-/// North Bridge specific SMM initialization in DXE\r
+/// North Bridge specific SMM initialization in DXE.\r
///\r
#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)\r
\r
///\r
-/// Initialization of the South Bridge specific UEFI Runtime Services\r
+/// Initialization of the South Bridge specific UEFI Runtime Services.\r
///\r
#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)\r
\r
#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)\r
\r
///\r
-/// South Bridge specific SMM initialization in DXE\r
+/// South Bridge specific SMM initialization in DXE.\r
///\r
#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)\r
\r
///\r
-/// Initialization of the South Bridge devices\r
+/// Initialization of the South Bridge devices.\r
///\r
#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT (EFI_SUBCLASS_SPECIFIC|0x0000000a)\r
\r
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