MdePkg: Added ARM Aarch64 architecture support

[mirror_edk2.git] / MdePkg / Include / Protocol / DebugSupport.h

diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 8ba6c4909bddf6d03f2f72e971328d8bffbb5102..52c4042bacee3a457b53059e3a7d81332642a1da 100644 (file)
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -1,11 +1,13 @@
 /** @file\r
-  DebugSupport protocol and supporting definitions as defined in the UEFI2.0\r
+  DebugSupport protocol and supporting definitions as defined in the UEFI2.4\r
   specification.\r
 \r
   The DebugSupport protocol is used by source level debuggers to abstract the\r
   processor and handle context save and restore operations.\r
 \r
 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials are licensed and made available under \r
 the terms and conditions of the BSD License that accompanies this distribution.  \r
 The full text of the license may be found at\r
@@ -517,6 +519,97 @@ typedef struct {
   UINT32  IFAR;\r
 } EFI_SYSTEM_CONTEXT_ARM;\r
 \r
+\r
+///\r
+///  AARCH64 processor exception types.\r
+///\r
+#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS    0\r
+#define EXCEPT_AARCH64_IRQ                       1\r
+#define EXCEPT_AARCH64_FIQ                       2\r
+#define EXCEPT_AARCH64_SERROR                    3\r
+\r
+///\r
+/// For coding convenience, define the maximum valid ARM exception.\r
+///\r
+#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
+\r
+typedef struct {\r
+  // General Purpose Registers\r
+  UINT64  X0;\r
+  UINT64  X1;\r
+  UINT64  X2;\r
+  UINT64  X3;\r
+  UINT64  X4;\r
+  UINT64  X5;\r
+  UINT64  X6;\r
+  UINT64  X7;\r
+  UINT64  X8;\r
+  UINT64  X9;\r
+  UINT64  X10;\r
+  UINT64  X11;\r
+  UINT64  X12;\r
+  UINT64  X13;\r
+  UINT64  X14;\r
+  UINT64  X15;\r
+  UINT64  X16;\r
+  UINT64  X17;\r
+  UINT64  X18;\r
+  UINT64  X19;\r
+  UINT64  X20;\r
+  UINT64  X21;\r
+  UINT64  X22;\r
+  UINT64  X23;\r
+  UINT64  X24;\r
+  UINT64  X25;\r
+  UINT64  X26;\r
+  UINT64  X27;\r
+  UINT64  X28;\r
+  UINT64  FP;   // x29 - Frame pointer\r
+  UINT64  LR;   // x30 - Link Register\r
+  UINT64  SP;   // x31 - Stack pointer\r
+\r
+  // FP/SIMD Registers\r
+  UINT64  V0[2];\r
+  UINT64  V1[2];\r
+  UINT64  V2[2];\r
+  UINT64  V3[2];\r
+  UINT64  V4[2];\r
+  UINT64  V5[2];\r
+  UINT64  V6[2];\r
+  UINT64  V7[2];\r
+  UINT64  V8[2];\r
+  UINT64  V9[2];\r
+  UINT64  V10[2];\r
+  UINT64  V11[2];\r
+  UINT64  V12[2];\r
+  UINT64  V13[2];\r
+  UINT64  V14[2];\r
+  UINT64  V15[2];\r
+  UINT64  V16[2];\r
+  UINT64  V17[2];\r
+  UINT64  V18[2];\r
+  UINT64  V19[2];\r
+  UINT64  V20[2];\r
+  UINT64  V21[2];\r
+  UINT64  V22[2];\r
+  UINT64  V23[2];\r
+  UINT64  V24[2];\r
+  UINT64  V25[2];\r
+  UINT64  V26[2];\r
+  UINT64  V27[2];\r
+  UINT64  V28[2];\r
+  UINT64  V29[2];\r
+  UINT64  V30[2];\r
+  UINT64  V31[2];\r
+\r
+  UINT64  ELR;  // Exception Link Register\r
+  UINT64  SPSR; // Saved Processor Status Register\r
+  UINT64  FPSR; // Floating Point Status Register\r
+  UINT64  ESR;  // Exception syndrome register\r
+  UINT64  FAR;  // Fault Address Register\r
+} EFI_SYSTEM_CONTEXT_AARCH64;\r
+\r
+\r
 ///\r
 /// Universal EFI_SYSTEM_CONTEXT definition.\r
 ///\r
@@ -526,6 +619,7 @@ typedef union {
   EFI_SYSTEM_CONTEXT_X64  *SystemContextX64;\r
   EFI_SYSTEM_CONTEXT_IPF  *SystemContextIpf;\r
   EFI_SYSTEM_CONTEXT_ARM  *SystemContextArm;\r
+  EFI_SYSTEM_CONTEXT_AARCH64  *SystemContextAArch64;\r
 } EFI_SYSTEM_CONTEXT;\r
 \r
 //\r
@@ -566,7 +660,8 @@ typedef enum {
   IsaX64  = IMAGE_FILE_MACHINE_X64,            ///< 0x8664\r
   IsaIpf  = IMAGE_FILE_MACHINE_IA64,           ///< 0x0200\r
   IsaEbc  = IMAGE_FILE_MACHINE_EBC,            ///< 0x0EBC\r
-  IsaArm  = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED  ///< 0x01c2\r
+  IsaArm  = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
+  IsaAArch64  = IMAGE_FILE_MACHINE_ARM64       ///< 0xAA64\r
 } EFI_INSTRUCTION_SET_ARCHITECTURE;\r
 \r
 \r