Removed duplicate PalCallStatic functions in different libraries. Moved ReadItc and...

[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / IpfCache.c

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index 7e96d9b76a5d5559e66a8a57dd7d2d41259c8f21..0c6f0e4dc8b195e6ab19a339af8ddfd84a45cfdd 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -12,21 +12,6 @@
 \r
 **/\r
 \r
-typedef struct {\r
-  UINT64                            Status;\r
-  UINT64                            r9;\r
-  UINT64                            r10;\r
-  UINT64                            r11;\r
-} PAL_PROC_RETURN;\r
-\r
-PAL_PROC_RETURN\r
-PalCallStatic (\r
-  IN      CONST VOID                *PalEntryPoint,\r
-  IN      UINT64                    Arg1,\r
-  IN      UINT64                    Arg2,\r
-  IN      UINT64                    Arg3,\r
-  IN      UINT64                    Arg4\r
-  );\r
 \r
 /**\r
   Invalidates the entire instruction cache in cache coherency domain of the\r
@@ -45,6 +30,41 @@ InvalidateInstructionCache (
   PalCallStatic (NULL, 1, 1, 1, 0);\r
 }\r
 \r
+/**\r
+  Invalidates a range of instruction cache lines in the cache coherency domain\r
+  of the calling CPU.\r
+\r
+  Invalidates the instruction cache lines specified by Address and Length. If\r
+  Address is not aligned on a cache line boundary, then entire instruction\r
+  cache line containing Address is invalidated. If Address + Length is not\r
+  aligned on a cache line boundary, then the entire instruction cache line\r
+  containing Address + Length -1 is invalidated. This function may choose to\r
+  invalidate the entire instruction cache if that is more efficient than\r
+  invalidating the specified range. If Length is 0, the no instruction cache\r
+  lines are invalidated. Address is returned.\r
+\r
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+  @param  Address The base address of the instruction cache lines to\r
+                  invalidate. If the CPU is in a physical addressing mode, then\r
+                  Address is a physical address. If the CPU is in a virtual\r
+                  addressing mode, then Address is a virtual address.\r
+\r
+  @param  Length  The number of bytes to invalidate from the instruction cache.\r
+\r
+  @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+  IN      VOID                      *Address,\r
+  IN      UINTN                     Length\r
+  )\r
+{\r
+  return IpfInvalidateInstructionCacheRange (Address, Length);\r
+}\r
+\r
 /**\r
   Writes Back and Invalidates the entire data cache in cache coherency domain\r
   of the calling CPU.\r