MdePkg/BaseLib: Support IA32 processors without CLFLUSH

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / FlushCacheLine.c

diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
index d157fbfb67f53222b17857ad54a24975dadf4801..7ad12aba14cbbf07fb8d269ed3a4221b64bbe2be 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
@@ -1,11 +1,11 @@
 /** @file\r
   AsmFlushCacheLine function\r
 \r
-  Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
+  http://opensource.org/licenses/bsd-license.php.\r
 \r
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
@@ -36,9 +36,23 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress\r
   )\r
 {\r
+  //\r
+  // If the CPU does not support CLFLUSH instruction, \r
+  // then promote flush range to flush entire cache.\r
+  //\r
   _asm {\r
-    mov     eax, LinearAddress\r
+    mov     eax, 1\r
+    cpuid\r
+    test    edx, BIT19\r
+    jz      NoClflush\r
+    mov     eax, [esp + 4]\r
     clflush [eax]\r
+    jmp     Done\r
+NoClflush:\r
+    wbinvd\r
+Done:\r
   }\r
+  \r
+  return LinearAddress;\r
 }\r
 \r