MdePkg/BaseLib: Support IA32 processors without CLFLUSH

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / GccInline.c

diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 02af3f66464c5dc0286a3e53c3e4dc0b8eff717f..f52a1fe171f33c3fdd64a922dbca328771958c65 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1,7 +1,7 @@
 /** @file\r
   GCC inline implementation of BaseLib processor specific functions.\r
   \r
 /** @file\r
   GCC inline implementation of BaseLib processor specific functions.\r
   \r

-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r

   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r


@@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress\r
   )\r
 {\r
   IN      VOID                      *LinearAddress\r
   )\r
 {\r

+  UINT32  RegEdx;\r
+\r
+  //\r
+  // If the CPU does not support CLFLUSH instruction, \r
+  // then promote flush range to flush entire cache.\r
+  //\r
+  AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);\r
+  if ((RegEdx & BIT19) == 0) {\r
+    __asm__ __volatile__ ("wbinvd":::"memory");\r
+    return LinearAddress;\r
+  }\r
+\r
+\r

   __asm__ __volatile__ (\r
     "clflush (%0)"\r
     : "+a" (LinearAddress) \r
   __asm__ __volatile__ (\r
     "clflush (%0)"\r
     : "+a" (LinearAddress) \r


@@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
     : "memory"\r
     );\r
     \r
     : "memory"\r
     );\r
     \r

-    return LinearAddress;\r
+  return LinearAddress;\r

 }\r
 \r
 \r
 }\r
 \r
 \r