--- /dev/null
+/** @file\r
+ This file declares PciCfg PPI used to access PCI configuration space in PEI\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation \r
+ All rights reserved. This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ Module Name: PciCfg.h\r
+\r
+ @par Revision Reference:\r
+ This PPI is defined in PI\r
+ Version 1.00.\r
+\r
+**/\r
+\r
+#ifndef __PEI_PCI_CFG2_H__\r
+#define __PEI_PCI_CFG2_H__\r
+\r
+\r
+#define EFI_PEI_PCI_CFG2_PPI_GUID \\r
+ { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r
+\r
+\r
+typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r
+\r
+#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r
+ (((bus) << 24) | \\r
+ ((dev) << 16) | \\r
+ ((func) << 8) | \\r
+ ((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)));\r
+\r
+//\r
+// EFI_PEI_PCI_CFG_PPI_WIDTH\r
+//\r
+typedef enum {\r
+ EfiPeiPciCfgWidthUint8 = 0,\r
+ EfiPeiPciCfgWidthUint16 = 1,\r
+ EfiPeiPciCfgWidthUint32 = 2,\r
+ EfiPeiPciCfgWidthUint64 = 3,\r
+ EfiPeiPciCfgWidthMaximum\r
+} EFI_PEI_PCI_CFG_PPI_WIDTH;\r
+\r
+//\r
+// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r
+//\r
+typedef struct {\r
+ UINT8 Register;\r
+ UINT8 Function;\r
+ UINT8 Device;\r
+ UINT8 Bus;\r
+ UINT32 ExtendedRegister;\r
+} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r
+\r
+/**\r
+ Reads from or write to a given location in the PCI configuration space.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes. \r
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r
+\r
+ @param Address The physical address of the access. The format of \r
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r
+\r
+ @param Buffer A pointer to the buffer of data..\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r
+ time.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO) (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN CONST UINT64 Address,\r
+ IN OUT VOID *Buffer\r
+);\r
+\r
+\r
+/**\r
+ PCI read-modify-write operation.\r
+\r
+ @param PeiServices An indirect pointer to the PEI Services Table \r
+ published by the PEI Foundation.\r
+\r
+ @param This Pointer to local data for the interface.\r
+\r
+ @param Width The width of the access. Enumerated in bytes. Type\r
+ EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r
+\r
+ @param Address The physical address of the access.\r
+\r
+ @param SetBits Points to value to bitwise-OR with the read configuration value. \r
+\r
+ The size of the value is determined by Width.\r
+\r
+ @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value. \r
+ The size of the value is determined by Width.\r
+\r
+\r
+ @retval EFI_SUCCESS The function completed successfully.\r
+\r
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r
+\r
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting \r
+ the operation at this time.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW) (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r
+ IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN CONST UINT64 Address,\r
+ IN CONST VOID *SetBits,\r
+ IN CONST VOID *ClearBits\r
+);\r
+\r
+/**\r
+ @par Ppi Description:\r
+ The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI \r
+ controllers behind a PCI root bridge controller.\r
+\r
+ @param Read PCI read services. See the Read() function description.\r
+\r
+ @param Write PCI write services. See the Write() function description.\r
+\r
+ @param Modify PCI read-modify-write services. See the Modify() function description.\r
+\r
+ @param Segment The PCI bus segment which the specified functions will access.\r
+\r
+**/\r
+struct _EFI_PEI_PCI_CFG2_PPI {\r
+ EFI_PEI_PCI_CFG2_PPI_IO Read;\r
+ EFI_PEI_PCI_CFG2_PPI_IO Write;\r
+ EFI_PEI_PCI_CFG2_PPI_RW Modify;\r
+ UINT16 Segment;\r
+};\r
+\r
+\r
+extern EFI_GUID gEfiPciCfg2PpiGuid;\r
+\r
+#endif\r
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