+++ /dev/null
-/** @file\r
- PCI Library.\r
-\r
- Copyright (c) 2006, Intel Corporation<BR>\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- Module Name: PciLib.c\r
-\r
-**/\r
-\r
-//\r
-// Declare I/O Ports used to perform PCI Confguration Cycles\r
-//\r
-#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8\r
-#define PCI_CONFIGURATION_DATA_PORT 0xCFC\r
-\r
-//\r
-// Declare macro to convert PCI Library formatted address to CF8 formatted address\r
-//\r
-// PCI Library formatted address CF8 Formatted Address\r
-// ============================= ======================\r
-// Bits 00..11 Register Bits 00..07 Register\r
-// Bits 12..14 Function Bits 08..10 Function\r
-// Bits 15..19 Device Bits 11..15 Device\r
-// Bits 20..27 Bus Bits 16..23 Bus\r
-// Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)\r
-// Bits 31..31 Must be 1\r
-//\r
-\r
-/**\r
- Assert the validity of a PCI address. A valid PCI address should contain 1's\r
- only in the low 28 bits.\r
-\r
- @param A The address to validate.\r
- @param M Additional bits to assert to be zero.\r
-\r
-**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
- ASSERT (((A) & (~0xffff0ff | (M))) == 0)\r
-\r
-/**\r
- Convert a PCI Express address to PCI CF8 address.\r
-\r
- @param A The address to convert.\r
-\r
- @retval The coverted address.\r
-\r
-**/\r
-#define PCI_TO_CF8_ADDRESS(A) \\r
- ((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))\r
-\r
-/**\r
- Reads an 8-bit PCI configuration register.\r
-\r
- Reads and returns the 8-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8Read8 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));\r
-}\r
-\r
-/**\r
- Writes an 8-bit PCI configuration register.\r
-\r
- Writes the 8-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8Write8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoWrite8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r
- an 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8Or8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8And8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAnd8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
- value, followed a bitwise inclusive OR with another 8-bit value.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8AndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAndThenOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8BitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldRead8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit\r
- );\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 8-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8BitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldWrite8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 8-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8BitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 8-bit register.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 8-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8BitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAnd8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 8-bit port.\r
-\r
- Reads the 8-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 8-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 7, then ASSERT().\r
- If EndBit is greater than 7, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..7.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..7.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT8\r
-EFIAPI\r
-PciCf8BitFieldAndThenOr8(\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAndThenOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a 16-bit PCI configuration register.\r
-\r
- Reads and returns the 16-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8Read16 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));\r
-}\r
-\r
-/**\r
- Writes a 16-bit PCI configuration register.\r
-\r
- Writes the 16-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8Write16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoWrite16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r
- a 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8Or16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8And16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAnd16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
- value, followed a bitwise inclusive OR with another 16-bit value.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8AndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAndThenOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8BitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldRead16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit\r
- );\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 16-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8BitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldWrite16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 16-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8BitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 16-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8BitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAnd16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 16-bit port.\r
-\r
- Reads the 16-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 16-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 16-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 15, then ASSERT().\r
- If EndBit is greater than 15, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..15.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..15.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT16\r
-EFIAPI\r
-PciCf8BitFieldAndThenOr16(\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAndThenOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a 32-bit PCI configuration register.\r
-\r
- Reads and returns the 32-bit PCI configuration register specified by Address.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
-\r
- @return The read value from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8Read32 (\r
- IN UINTN Address\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoRead32 (PCI_CONFIGURATION_DATA_PORT);\r
-}\r
-\r
-/**\r
- Writes a 32-bit PCI configuration register.\r
-\r
- Writes the 32-bit PCI configuration register specified by Address with the\r
- value specified by Value. Value is returned. This function must guarantee\r
- that all PCI read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param Value The value to write.\r
-\r
- @return The value written to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8Write32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoWrite32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r
- a 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8Or32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8And32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAnd32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
- value, followed a bitwise inclusive OR with another 32-bit value.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData,\r
- performs a bitwise inclusive OR between the result of the AND operation and\r
- the value specified by OrData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
-\r
- @param Address Address that encodes the PCI Bus, Device, Function and\r
- Register.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8AndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAndThenOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field of a PCI configuration register.\r
-\r
- Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
- specified by the StartBit and the EndBit. The value of the bit field is\r
- returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to read.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
-\r
- @return The value of the bit field read from the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8BitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldRead32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit\r
- );\r
-}\r
-\r
-/**\r
- Writes a bit field to a PCI configuration register.\r
-\r
- Writes Value to the bit field of the PCI configuration register. The bit\r
- field is specified by the StartBit and the EndBit. All other bits in the\r
- destination PCI configuration register are preserved. The new value of the\r
- 32-bit register is returned.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param Value New value of the bit field.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8BitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldWrite32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
- writes the result back to the bit field in the 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise inclusive OR between the read result and the value specified by\r
- OrData, and writes the result to the 32-bit PCI configuration register\r
- specified by Address. The value written to the PCI configuration register is\r
- returned. This function must guarantee that all PCI read and write operations\r
- are serialized. Extra left bits in OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param OrData The value to OR with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8BitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
- AND, and writes the result back to the bit field in the 32-bit register.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND between the read result and the value specified by AndData, and\r
- writes the result to the 32-bit PCI configuration register specified by\r
- Address. The value written to the PCI configuration register is returned.\r
- This function must guarantee that all PCI read and write operations are\r
- serialized. Extra left bits in AndData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8BitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAnd32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
-}\r
-\r
-/**\r
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
- bitwise inclusive OR, and writes the result back to the bit field in the\r
- 32-bit port.\r
-\r
- Reads the 32-bit PCI configuration register specified by Address, performs a\r
- bitwise AND followed by a bitwise inclusive OR between the read result and\r
- the value specified by AndData, and writes the result to the 32-bit PCI\r
- configuration register specified by Address. The value written to the PCI\r
- configuration register is returned. This function must guarantee that all PCI\r
- read and write operations are serialized. Extra left bits in both AndData and\r
- OrData are stripped.\r
-\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
- If Address is not aligned on a 32-bit boundary, then ASSERT().\r
- If the register specified by Address >= 0x100, then ASSERT().\r
- If StartBit is greater than 31, then ASSERT().\r
- If EndBit is greater than 31, then ASSERT().\r
- If EndBit is less than StartBit, then ASSERT().\r
-\r
- @param Address PCI configuration register to write.\r
- @param StartBit The ordinal of the least significant bit in the bit field.\r
- Range 0..31.\r
- @param EndBit The ordinal of the most significant bit in the bit field.\r
- Range 0..31.\r
- @param AndData The value to AND with the PCI configuration register.\r
- @param OrData The value to OR with the result of the AND operation.\r
-\r
- @return The value written back to the PCI configuration register.\r
-\r
-**/\r
-UINT32\r
-EFIAPI\r
-PciCf8BitFieldAndThenOr32(\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
-{\r
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
- IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAndThenOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
-}\r
-\r
-/**\r
- Reads a range of PCI configuration registers into a caller supplied buffer.\r
-\r
- Reads the range of PCI configuration registers specified by StartAddress and\r
- Size into the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be read. Size is\r
- returned. When possible 32-bit PCI configuration read cycles are used to read\r
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
- and 16-bit PCI configuration read cycles may be used at the beginning and the\r
- end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by StartAddress >= 0x100, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer receiving the data read.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciCf8ReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
-\r
- if (Size == 0) {\r
- return Size;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Read a byte if StartAddress is byte aligned\r
- //\r
- *(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Read a word if StartAddress is word aligned\r
- //\r
- *(volatile UINT16 *)Buffer = PciCf8Read16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Read as many double words as possible\r
- //\r
- *(volatile UINT32 *)Buffer = PciCf8Read32 (StartAddress);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Read the last remaining word if exist\r
- //\r
- *(volatile UINT16 *)Buffer = PciCf8Read16 (StartAddress);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Read the last remaining byte if exist\r
- //\r
- *(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
-\r
-/**\r
- Copies the data in a caller supplied buffer to a specified range of PCI\r
- configuration space.\r
-\r
- Writes the range of PCI configuration registers specified by StartAddress and\r
- Size from the buffer specified by Buffer. This function only allows the PCI\r
- configuration registers from a single PCI function to be written. Size is\r
- returned. When possible 32-bit PCI configuration write cycles are used to\r
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
- and the end of the range.\r
-\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
- If the register specified by StartAddress >= 0x100, then ASSERT().\r
- If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r
- If Size > 0 and Buffer is NULL, then ASSERT().\r
-\r
- @param StartAddress Starting address that encodes the PCI Bus, Device,\r
- Function and Register.\r
- @param Size Size in bytes of the transfer.\r
- @param Buffer Pointer to a buffer containing the data to write.\r
-\r
- @return Size\r
-\r
-**/\r
-UINTN\r
-EFIAPI\r
-PciCf8WriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
-{\r
- UINTN ReturnValue;\r
-\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
-\r
- if (Size == 0) {\r
- return 0;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Write a byte if StartAddress is byte aligned\r
- //\r
- PciCf8Write8 (StartAddress, *(UINT8*)Buffer);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Write a word if StartAddress is word aligned\r
- //\r
- PciCf8Write16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Write as many double words as possible\r
- //\r
- PciCf8Write32 (StartAddress, *(UINT32*)Buffer);\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Write the last remaining word if exist\r
- //\r
- PciCf8Write16 (StartAddress, *(UINT16*)Buffer);\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Write the last remaining byte if exist\r
- //\r
- PciCf8Write8 (StartAddress, *(UINT8*)Buffer);\r
- }\r
-\r
- return ReturnValue;\r
-}\r
projects / mirror_edk2.git / blobdiff