Cleanup SerailIO drivers to have a device path and use PCD settings for various stuff...

[mirror_edk2.git] / Omap35xxPkg / InterruptDxe / HardwareInterrupt.c

diff --git a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
index feb5b26dfe719794ffc108edc7339f54012951f8..6e30eb7e67e1f7a14e3e3b06af7f0312c5f457ea 100644 (file)
--- a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
+++ b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
@@ -54,10 +54,10 @@ ExitBootServicesEvent (
   )\r
 {\r
   // Disable all interrupts\r
-  MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);\r
-  MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);\r
-  MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);\r
-  MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+  MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
+  MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
+  MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
+  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
 }\r
 \r
 /**\r
@@ -125,7 +125,7 @@ EnableInterruptSource (
   Bank = Source / 32;\r
   Bit  = 1UL << (Source % 32);\r
   \r
-  MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);\r
+  MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
   \r
   return EFI_SUCCESS;\r
 }\r
@@ -159,7 +159,7 @@ DisableInterruptSource(
   Bank = Source / 32;\r
   Bit  = 1UL << (Source % 32);\r
   \r
-  MmioWrite32(INTCPS_MIR_SET(Bank), Bit);\r
+  MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
   \r
   return EFI_SUCCESS;\r
 }\r
@@ -235,7 +235,7 @@ IrqInterruptHandler (
   Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
 \r
   // Needed to prevent infinite nesting when Time Driver lowers TPL\r
-  MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
 \r
   InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
   if (InterruptHandler != NULL) {\r
@@ -244,7 +244,7 @@ IrqInterruptHandler (
   }\r
   \r
   // Needed to clear after running the handler\r
-  MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
 }\r
 \r
 //\r
@@ -316,10 +316,10 @@ InterruptDxeInitialize (
   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
 \r
   // Make sure all interrupts are disabled by default.\r
-  MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);\r
-  MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);\r
-  MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);\r
-  MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+  MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
+  MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
+  MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
+  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
  \r
   Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
                                                   &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,\r