ARM Packages: Removed trailing spaces

[mirror_edk2.git] / Omap35xxPkg / InterruptDxe / HardwareInterrupt.c

diff --git a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
index 5040c4b152c568045180d3dc647d92955df1d758..e9d84aeabb698960d4936c4e95a42101e8b4399b 100644 (file)
--- a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
+++ b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
@@ -1,8 +1,8 @@
 /** @file\r
-  Handle OMAP35xx interrupt controller \r
+  Handle OMAP35xx interrupt controller\r
 \r
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-  \r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -38,7 +38,7 @@ HARDWARE_INTERRUPT_HANDLER  gRegisteredInterruptHandlers[INT_NROF_VECTORS];
 \r
 /**\r
   Shutdown our hardware\r
-  \r
+\r
   DXE Core will disable interrupts and turn off the timer and disable interrupts\r
   after all the event handlers have run.\r
 \r
@@ -83,16 +83,16 @@ RegisterInterruptSource (
   if (Source > MAX_VECTOR) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
-  } \r
-  \r
+  }\r
+\r
   if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {\r
     // This vector has been programmed as FIQ so we can't use it for IRQ\r
-    // EFI does not use FIQ, but the debugger can use it to check for \r
+    // EFI does not use FIQ, but the debugger can use it to check for\r
     // ctrl-c. So this ASSERT means you have a conflict with the debug agent\r
     ASSERT (FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
-  \r
+\r
   if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -125,17 +125,17 @@ EnableInterruptSource (
 {\r
   UINTN Bank;\r
   UINTN Bit;\r
-  \r
+\r
   if (Source > MAX_VECTOR) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
-  \r
+\r
   Bank = Source / 32;\r
   Bit  = 1UL << (Source % 32);\r
-  \r
+\r
   MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
-  \r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -159,17 +159,17 @@ DisableInterruptSource (
 {\r
   UINTN Bank;\r
   UINTN Bit;\r
-  \r
+\r
   if (Source > MAX_VECTOR) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
-  \r
+\r
   Bank = Source / 32;\r
   Bit  = 1UL << (Source % 32);\r
-  \r
+\r
   MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
-  \r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -196,11 +196,11 @@ GetInterruptSourceState (
 {\r
   UINTN Bank;\r
   UINTN Bit;\r
-  \r
+\r
   if (InterruptState == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
-  \r
+\r
   if (Source > MAX_VECTOR) {\r
     ASSERT(FALSE);\r
     return EFI_UNSUPPORTED;\r
@@ -208,18 +208,18 @@ GetInterruptSourceState (
 \r
   Bank = Source / 32;\r
   Bit  = 1UL << (Source % 32);\r
-    \r
+\r
   if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {\r
     *InterruptState = FALSE;\r
   } else {\r
     *InterruptState = TRUE;\r
   }\r
-  \r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
 /**\r
-  Signal to the hardware that the End Of Intrrupt state \r
+  Signal to the hardware that the End Of Intrrupt state\r
   has been reached.\r
 \r
   @param This     Instance pointer for this protocol\r
@@ -262,19 +262,19 @@ IrqInterruptHandler (
 {\r
   UINT32                     Vector;\r
   HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
-  \r
+\r
   Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
 \r
   // Needed to prevent infinite nesting when Time Driver lowers TPL\r
   MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
   ArmDataSyncronizationBarrier ();\r
-  \r
+\r
   InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
   if (InterruptHandler != NULL) {\r
     // Call the registered interrupt handler.\r
     InterruptHandler (Vector, SystemContext);\r
   }\r
-  \r
+\r
   // Needed to clear after running the handler\r
   MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
   ArmDataSyncronizationBarrier ();\r
@@ -324,12 +324,12 @@ InterruptDxeInitialize (
   MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
   MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
   MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
- \r
+\r
   Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
                                                   &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,\r
                                                   NULL);\r
   ASSERT_EFI_ERROR(Status);\r
-  \r
+\r
   //\r
   // Get the CPU protocol that this driver requires.\r
   //\r