+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#include <Uefi.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/TimerLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/OmapLib.h>\r
-\r
-#include <Omap3530/Omap3530.h>\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-TimerConstructor (\r
- VOID\r
- )\r
-{\r
- UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);\r
- UINT32 TimerBaseAddress = TimerBase(Timer);\r
-\r
- if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {\r
- // Set source clock for GPT3 & GPT4 to SYS_CLK\r
- MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r
-\r
- // Set count & reload registers\r
- MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
- MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
-\r
- // Disable interrupts\r
- MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
-\r
- // Start Timer\r
- MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
-\r
- // Disable OMAP Watchdog timer (WDT2)\r
- MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r
- DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r
- MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
- )\r
-{\r
- UINT64 NanoSeconds;\r
-\r
- NanoSeconds = MultU64x32(MicroSeconds, 1000);\r
-\r
- while (NanoSeconds > (UINTN)-1) {\r
- NanoSecondDelay((UINTN)-1);\r
- NanoSeconds -= (UINTN)-1;\r
- }\r
-\r
- NanoSecondDelay(NanoSeconds);\r
-\r
- return MicroSeconds;\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
- )\r
-{\r
- UINT32 Delay;\r
- UINT32 StartTime;\r
- UINT32 CurrentTime;\r
- UINT32 ElapsedTime;\r
- UINT32 TimerCountRegister;\r
-\r
- Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1;\r
-\r
- TimerCountRegister = TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR;\r
-\r
- StartTime = MmioRead32 (TimerCountRegister);\r
-\r
- do\r
- {\r
- CurrentTime = MmioRead32 (TimerCountRegister);\r
- ElapsedTime = CurrentTime - StartTime;\r
- } while (ElapsedTime < Delay);\r
-\r
- NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds);\r
-\r
- return NanoSeconds;\r
-}\r
-\r
-UINT64\r
-EFIAPI\r
-GetPerformanceCounter (\r
- VOID\r
- )\r
-{\r
- return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);\r
-}\r
-\r
-UINT64\r
-EFIAPI\r
-GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue, OPTIONAL\r
- OUT UINT64 *EndValue OPTIONAL\r
- )\r
-{\r
- if (StartValue != NULL) {\r
- // Timer starts with the reload value\r
- *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);\r
- }\r
-\r
- if (EndValue != NULL) {\r
- // Timer counts up to 0xFFFFFFFF\r
- *EndValue = 0xFFFFFFFF;\r
- }\r
-\r
- return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz);\r
-}\r
-\r
-/**\r
- Converts elapsed ticks of performance counter to time in nanoseconds.\r
-\r
- This function converts the elapsed ticks of running performance counter to\r
- time value in unit of nanoseconds.\r
-\r
- @param Ticks The number of elapsed ticks of running performance counter.\r
-\r
- @return The elapsed time in nanoseconds.\r
-\r
-**/\r
-UINT64\r
-EFIAPI\r
-GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
- )\r
-{\r
- UINT32 Period;\r
-\r
- Period = PcdGet32 (PcdEmbeddedPerformanceCounterPeriodInNanoseconds);\r
-\r
- return (Ticks * Period);\r
-}\r