ARM Packages: Removed trailing spaces

[mirror_edk2.git] / Omap35xxPkg / Library / OmapDmaLib / OmapDmaLib.c

diff --git a/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c b/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
index d1183129a604a53427bf06f10f84c03bae8a39aa..41cfefbebc11d201c46ef766d2c95ae8513d7069 100755 (executable)
--- a/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
+++ b/Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
@@ -1,9 +1,9 @@
 /** @file\r
   Abstractions for simple OMAP DMA channel.\r
-  \r
+\r
 \r
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-  \r
+\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -22,16 +22,16 @@
 #include <Omap3530/Omap3530.h>\r
 \r
 \r
-/**                                                                 \r
+/**\r
   Configure OMAP DMA Channel\r
-            \r
+\r
   @param  Channel               DMA Channel to configure\r
-  @param  Dma4                  Pointer to structure used to initialize DMA registers for the Channel                                                \r
-                                  \r
+  @param  Dma4                  Pointer to structure used to initialize DMA registers for the Channel\r
+\r
   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
   @retval EFI_INVALID_PARAMETER Channel is not valid\r
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.\r
-                                   \r
+\r
 **/\r
 EFI_STATUS\r
 EFIAPI\r
@@ -50,13 +50,13 @@ EnableDmaChannel (
   /* 1) Configure the transfer parameters in the logical DMA registers */\r
   /*-------------------------------------------------------------------*/\r
 \r
-  /* a) Set the data type CSDP[1:0], the Read/Write Port access type \r
-        CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19], \r
+  /* a) Set the data type CSDP[1:0], the Read/Write Port access type\r
+        CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],\r
         write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */\r
-  \r
+\r
   // Read CSDP\r
   RegVal = MmioRead32 (DMA4_CSDP (Channel));\r
-  \r
+\r
   // Build reg\r
   RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );\r
   RegVal = ((RegVal & ~(0x3 <<  7)) | (DMA4->ReadPortAccessType << 7));\r
@@ -68,23 +68,23 @@ EnableDmaChannel (
   RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));\r
   // Write CSDP\r
   MmioWrite32 (DMA4_CSDP (Channel), RegVal);\r
-  \r
+\r
   /* b) Set the number of element per frame CEN[23:0]*/\r
   MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);\r
- \r
+\r
   /* c) Set the number of frame per block CFN[15:0]*/\r
   MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);\r
-  \r
+\r
   /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/\r
   MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);\r
   MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);\r
-  \r
+\r
   /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],\r
         read/write priority CCR[6]/CCR[26]\r
-        I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to \r
+        I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to\r
         LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber\r
   */\r
-  \r
+\r
   // Read CCR\r
   RegVal = MmioRead32 (DMA4_CCR (Channel));\r
 \r
@@ -95,13 +95,13 @@ EnableDmaChannel (
   RegVal  = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));\r
   RegVal  = ((RegVal & ~(0x1 <<  6)) | (DMA4->ReadPriority << 6));\r
   RegVal  = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));\r
-  \r
+\r
   // Write CCR\r
   MmioWrite32 (DMA4_CCR (Channel), RegVal);\r
-  \r
+\r
   /* f)- Set the source element index CSEI[15:0]*/\r
   MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);\r
-  \r
+\r
   /* - Set the source frame index CSFI[15:0]*/\r
   MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);\r
 \r
@@ -111,7 +111,7 @@ EnableDmaChannel (
 \r
   /* - Set the destination frame index CDFI[31:0]*/\r
   MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
- \r
+\r
   MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
 \r
   // Enable all the status bits since we are polling\r
@@ -126,17 +126,17 @@ EnableDmaChannel (
   return EFI_SUCCESS;\r
 }\r
 \r
-/**                                                                 \r
+/**\r
   Turn of DMA channel configured by EnableDma().\r
-            \r
+\r
   @param  Channel               DMA Channel to configure\r
   @param  SuccesMask            Bits in DMA4_CSR register indicate EFI_SUCCESS\r
   @param  ErrorMask             Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r
-                                  \r
+\r
   @retval EFI_SUCCESS           DMA hardware disabled\r
   @retval EFI_INVALID_PARAMETER Channel is not valid\r
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.\r
-                                   \r
+\r
 **/\r
 EFI_STATUS\r
 EFIAPI\r
@@ -168,7 +168,7 @@ DisableDmaChannel (
   MmioWrite32 (DMA4_CICR (Channel), 0);\r
   MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);\r
 \r
-  MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE)); \r
+  MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));\r
   return Status;\r
 }\r
 \r